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authorTom Stellard <tstellar@redhat.com>2018-05-05 02:52:41 +0000
committerTom Stellard <tstellar@redhat.com>2018-05-05 02:52:41 +0000
commitf716fede92a78b64eac24a3261d118b726d9610d (patch)
tree568fbec8cb9f75b7c08052179748d1d08de48f0a
parent294016b826dd563cfa9b8e7b536cde9b5a2b2cbf (diff)
downloadbcm5719-llvm-f716fede92a78b64eac24a3261d118b726d9610d.tar.gz
bcm5719-llvm-f716fede92a78b64eac24a3261d118b726d9610d.zip
GlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm
Summary: AMDGPU will need this to enable the TableGen'd GlobalISel selector. Reviewers: dsanders, aditya_nandakumar Reviewed By: dsanders Subscribers: rovka, kristof.beyls, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D45990 llvm-svn: 331579
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h6
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h17
2 files changed, 23 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
index 90e213f750d..1dee6d12484 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
@@ -248,6 +248,12 @@ enum {
/// The operand index is implicitly 1.
GIR_CopyConstantAsSImm,
+ /// Render a G_FCONSTANT operator as a sign-extended immediate.
+ /// - NewInsnID - Instruction ID to modify
+ /// - OldInsnID - Instruction ID to copy from
+ /// The operand index is implicitly 1.
+ GIR_CopyFConstantAsFPImm,
+
/// Constrain an instruction operand to a register class.
/// - InsnID - Instruction ID to modify
/// - OpIdx - Operand index
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
index f7593ba6ef2..415ae74ed7f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
@@ -662,6 +662,23 @@ bool InstructionSelector::executeMatchTable(
break;
}
+ // TODO: Needs a test case once we have a pattern that uses this.
+ case GIR_CopyFConstantAsFPImm: {
+ int64_t NewInsnID = MatchTable[CurrentIdx++];
+ int64_t OldInsnID = MatchTable[CurrentIdx++];
+ assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
+ assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
+ if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
+ OutMIs[NewInsnID].addFPImm(
+ State.MIs[OldInsnID]->getOperand(1).getFPImm());
+ else
+ llvm_unreachable("Expected FPImm operand");
+ DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+ dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
+ << NewInsnID << "], MIs[" << OldInsnID << "])\n");
+ break;
+ }
+
case GIR_CustomRenderer: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OldInsnID = MatchTable[CurrentIdx++];
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