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authorQuentin Colombet <qcolombet@apple.com>2016-10-13 00:12:01 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-10-13 00:12:01 +0000
commitdb643d90918857921ae49c2c719c3a502a7138cc (patch)
treed31e37d73baa142908a6b12e09263c9aeca9192e
parentf760799c4013823a1f82a66316f4bd96fd699d06 (diff)
downloadbcm5719-llvm-db643d90918857921ae49c2c719c3a502a7138cc.tar.gz
bcm5719-llvm-db643d90918857921ae49c2c719c3a502a7138cc.zip
[AArch64][MachineLegalizer] Mark more G_BITCAST as legal.
Basically any vector types that fits in a 32-bit register is also valid as far as copies are concerned. llvm-svn: 284089
-rw-r--r--llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp9
-rw-r--r--llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir3
2 files changed, 11 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 4f921e8d8ef..46261bca67c 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -181,14 +181,21 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
setAction({G_BITCAST, 1, Ty}, Legal);
}
+ // For the sake of copying bits around, the type does not really
+ // matter as long as it fits a register.
for (int EltSize = 8; EltSize <= 64; EltSize *= 2) {
setAction({G_BITCAST, 0, LLT::vector(128/EltSize, EltSize)}, Legal);
setAction({G_BITCAST, 1, LLT::vector(128/EltSize, EltSize)}, Legal);
- if (EltSize == 64)
+ if (EltSize >= 64)
continue;
setAction({G_BITCAST, 0, LLT::vector(64/EltSize, EltSize)}, Legal);
setAction({G_BITCAST, 1, LLT::vector(64/EltSize, EltSize)}, Legal);
+ if (EltSize >= 32)
+ continue;
+
+ setAction({G_BITCAST, 0, LLT::vector(32/EltSize, EltSize)}, Legal);
+ setAction({G_BITCAST, 1, LLT::vector(32/EltSize, EltSize)}, Legal);
}
computeTables();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 1817a910151..97a31d36577 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -48,6 +48,7 @@ registers:
- { id: 31, class: _ }
- { id: 32, class: _ }
- { id: 33, class: _ }
+ - { id: 34, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@@ -127,4 +128,6 @@ body: |
%30(<2 x s32>) = G_BITCAST %9
%31(s64) = G_BITCAST %30
%32(s32) = G_BITCAST %15
+ %33(<4 x s8>) = G_BITCAST %15
+ %34(<2 x s16>) = G_BITCAST %15
...
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