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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-02-26 20:56:25 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-02-26 20:56:25 +0000 |
| commit | da1628eb679d2921e5d683e51cc9ecf6e5750295 (patch) | |
| tree | b925208af4615754ff253253172bae28cb67d0af | |
| parent | ddc181d2561b14b95e7b3afbacaa0e55d16ea733 (diff) | |
| download | bcm5719-llvm-da1628eb679d2921e5d683e51cc9ecf6e5750295.tar.gz bcm5719-llvm-da1628eb679d2921e5d683e51cc9ecf6e5750295.zip | |
[AMDGPU] Fixed hang during DAG combine
SITargetLowering::reassociateScalarOps() does not touch constants
so that DAGCombiner::ReassociateOps() does not revert the combine.
However a global address is not a ConstantSDNode.
Switched to the method used by DAGCombiner::ReassociateOps() itself
to detect constants.
Differential Revision: https://reviews.llvm.org/D58695
llvm-svn: 354926
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll | 16 |
2 files changed, 18 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 83d7711e801..adb9ed41662 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -8477,7 +8477,8 @@ SDValue SITargetLowering::reassociateScalarOps(SDNode *N, // If either operand is constant this will conflict with // DAGCombiner::ReassociateOps(). - if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) + if (DAG.isConstantIntBuildVectorOrConstantInt(Op0) || + DAG.isConstantIntBuildVectorOrConstantInt(Op1)) return SDValue(); SDLoc SL(N); diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll index 32b4a3390ba..cd1ea6d0ed5 100644 --- a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll +++ b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll @@ -109,5 +109,21 @@ bb: ret void } +@var = common hidden local_unnamed_addr addrspace(1) global [4 x i32] zeroinitializer, align 4 + +; GCN-LABEL: reassoc_i32_ga: +; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@lo+4 +; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@hi+4 +; GCN: s_endpgm +define amdgpu_kernel void @reassoc_i32_ga(i64 %x) { +bb: + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() + %t64 = zext i32 %tid to i64 + %add1 = getelementptr [4 x i32], [4 x i32] addrspace(1)* @var, i64 0, i64 %t64 + %add2 = getelementptr i32, i32 addrspace(1)* %add1, i64 %x + store volatile i32 1, i32 addrspace(1)* %add2, align 4 + ret void +} + declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.y() |
