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| author | Craig Topper <craig.topper@intel.com> | 2018-11-16 07:13:34 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-16 07:13:34 +0000 |
| commit | bac7d9735aae5ad6765f532ded197711f0cf876c (patch) | |
| tree | c62e8b602c11d2899db89b465b45f93af67dab1e | |
| parent | bf46e7410c8a1d26c4a434261baaae28a904d657 (diff) | |
| download | bcm5719-llvm-bac7d9735aae5ad6765f532ded197711f0cf876c.tar.gz bcm5719-llvm-bac7d9735aae5ad6765f532ded197711f0cf876c.zip | |
[LegalizeVectorTypes] Teach WidenVecRes_Convert to turn ANY_EXTEND into ANY_EXTEND_VECTOR_INREG when the input and output types need to be widened to the same width.
If we don't do it here, DAGCombine will just end up creating it from the scalar any_extend+build_vector so might as well save a step.
llvm-svn: 347034
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 899a7be5d6e..a1c7559170f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2831,6 +2831,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { // If both input and result vector types are of same width, extend // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which // accepts fewer elements in the result than in the input. + if (Opcode == ISD::ANY_EXTEND) + return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); if (Opcode == ISD::SIGN_EXTEND) return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); if (Opcode == ISD::ZERO_EXTEND) |
