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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-14 18:00:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-14 18:00:31 +0000 |
| commit | b218202586444b93dcdccab24b1ca093ee61211d (patch) | |
| tree | c21fdb35fec8b06772e188ec5a43992c5662d10c | |
| parent | 8d375cef55625065b1cf2bc5dadeaf91d6e900e6 (diff) | |
| download | bcm5719-llvm-b218202586444b93dcdccab24b1ca093ee61211d.tar.gz bcm5719-llvm-b218202586444b93dcdccab24b1ca093ee61211d.zip | |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/arm_instructions.s | 2 |
3 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 5d646e73499..7e5d1363dcb 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3317,12 +3317,16 @@ def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; // ISB has only full system option -def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>, +def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, + "isb", "\t$opt", []>, Requires<[IsARM, HasDB]> { + bits<4> opt; let Inst{31-4} = 0xf57ff06; - let Inst{3-0} = 0b1111; + let Inst{3-0} = opt; } +def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; + let usesCustomInserter = 1 in { let Uses = [CPSR] in { def ATOMIC_LOAD_ADD_I8 : PseudoInst< diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index fe165b04b43..581d877a203 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -3380,7 +3380,7 @@ static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - if (Opcode == ARM::DMB || Opcode == ARM::DSB) { + if (Opcode == ARM::DMB || Opcode == ARM::DSB || Opcode == ARM::ISB) { // Inst{3-0} encodes the memory barrier option for the variants. unsigned opt = slice(insn, 3, 0); switch (opt) { diff --git a/llvm/test/MC/ARM/arm_instructions.s b/llvm/test/MC/ARM/arm_instructions.s index eac38ac4951..86313063c66 100644 --- a/llvm/test/MC/ARM/arm_instructions.s +++ b/llvm/test/MC/ARM/arm_instructions.s @@ -139,7 +139,7 @@ @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] bkpt #10 -@ CHECK: isb @ encoding: [0x6f,0xf0,0x7f,0xf5] +@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5] isb @ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] mrs r8, cpsr |
