[AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)

Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D47365

llvm-svn: 333422

6 files changed, 119 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index b3c000430d1..513b4f7a257 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -472,6 +472,8 @@ let Predicates = [HasSVE] in {
   defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">;
   defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
 
+  defm LSR_ZPmZ  : sve_int_bin_pred_shift_1<0b001, "lsr">;
+  defm LSL_ZPmZ  : sve_int_bin_pred_shift_1<0b011, "lsl">;
 
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index b61ecfaa34f..7f0dbdc89d5 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -598,6 +598,39 @@ multiclass sve_int_index_rr<string asm> {
   def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
   def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
 }
+//
+//===----------------------------------------------------------------------===//
+// SVE Bitwise Shift - Predicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_bin_pred_shift_1<bits<2> sz8_64, bits<3> opc, string asm,
+                               ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+  asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Zdn;
+  bits<5> Zm;
+  let Inst{31-24} = 0b00000100;
+  let Inst{23-22} = sz8_64;
+  let Inst{21-19} = 0b010;
+  let Inst{18-16} = opc;
+  let Inst{15-13} = 0b100;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zm;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_bin_pred_shift_1<bits<3> opc, string asm> {
+  def _B : sve_int_bin_pred_shift_1<0b00, opc, asm, ZPR8>;
+  def _H : sve_int_bin_pred_shift_1<0b01, opc, asm, ZPR16>;
+  def _S : sve_int_bin_pred_shift_1<0b10, opc, asm, ZPR32>;
+  def _D : sve_int_bin_pred_shift_1<0b11, opc, asm, ZPR64>;
+}
+
 
 //===----------------------------------------------------------------------===//
 // SVE Shift by Immediate - Unpredicated Group
diff --git a/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s b/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s
index cbcd713ec0e..255f4f99700 100644
--- a/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s
@@ -39,3 +39,21 @@ lsl z25.d, z16.d, #64
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
 // CHECK-NEXT: lsl z25.d, z16.d, #64
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Source and Destination Registers must match
+lsl z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: lsl z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element sizes must match
+lsl z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Predicate not in restricted predicate range
+lsl z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/lsl.s b/llvm/test/MC/AArch64/SVE/lsl.s
index eb0e6c5ce3e..c5d84822824 100644
--- a/llvm/test/MC/AArch64/SVE/lsl.s
+++ b/llvm/test/MC/AArch64/SVE/lsl.s
@@ -54,3 +54,27 @@ lsl     z31.d, z31.d, #63
 // CHECK-ENCODING: [0xff,0x9f,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 9f ff 04 <unknown>
+
+lsl     z0.b, p0/m, z0.b, z0.b
+// CHECK-INST: lsl     z0.b, p0/m, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x80,0x13,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 13 04 <unknown>
+
+lsl     z0.h, p0/m, z0.h, z0.h
+// CHECK-INST: lsl     z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x53,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 53 04 <unknown>
+
+lsl     z0.s, p0/m, z0.s, z0.s
+// CHECK-INST: lsl     z0.s, p0/m, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x93,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 93 04 <unknown>
+
+lsl     z0.d, p0/m, z0.d, z0.d
+// CHECK-INST: lsl     z0.d, p0/m, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x80,0xd3,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 d3 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s b/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s
index 7f29a5378b2..3b353239a34 100644
--- a/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s
@@ -39,3 +39,21 @@ lsr z26.d, z26.d, #65
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
 // CHECK-NEXT: lsr z26.d, z26.d, #65
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Source and Destination Registers must match
+lsr z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: lsr z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element sizes must match
+lsr z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Predicate not in restricted predicate range
+lsr z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/lsr.s b/llvm/test/MC/AArch64/SVE/lsr.s
index a61ce6a1879..fcb0a234ed2 100644
--- a/llvm/test/MC/AArch64/SVE/lsr.s
+++ b/llvm/test/MC/AArch64/SVE/lsr.s
@@ -54,3 +54,27 @@ lsr     z31.d, z31.d, #1
 // CHECK-ENCODING: [0xff,0x97,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 97 ff 04 <unknown>
+
+lsr     z0.b, p0/m, z0.b, z0.b
+// CHECK-INST: lsr     z0.b, p0/m, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x80,0x11,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 11 04 <unknown>
+
+lsr     z0.h, p0/m, z0.h, z0.h
+// CHECK-INST: lsr     z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x51,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 51 04 <unknown>
+
+lsr     z0.s, p0/m, z0.s, z0.s
+// CHECK-INST: lsr     z0.s, p0/m, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x91,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 91 04 <unknown>
+
+lsr     z0.d, p0/m, z0.d, z0.d
+// CHECK-INST: lsr     z0.d, p0/m, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x80,0xd1,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 d1 04 <unknown>