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| author | Sam Kolton <Sam.Kolton@amd.com> | 2017-04-07 10:53:12 +0000 |
|---|---|---|
| committer | Sam Kolton <Sam.Kolton@amd.com> | 2017-04-07 10:53:12 +0000 |
| commit | 6e79529db4e81cc99ec28359b6a32a9c3fece184 (patch) | |
| tree | d9cf5d457741b62ae806fb8f58e4d799f483bb2d | |
| parent | 3c608448e1a5c162697e2478a264b4596f9cf2ad (diff) | |
| download | bcm5719-llvm-6e79529db4e81cc99ec28359b6a32a9c3fece184.tar.gz bcm5719-llvm-6e79529db4e81cc99ec28359b6a32a9c3fece184.zip | |
[AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passes
Summary:
Difference beetween PreRegAlloc() and MachineSSAOptimization() are that the former is run despite of -O0 optimization level. In my undestanding SiShrinkInstructions and SDWAPeephole shouldn't run when optimizations are disabled.
With this change order of passes will not change.
Reviewers: arsenm, vpykhtin, rampitec
Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D31705
llvm-svn: 299757
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 80feef384be..9cd8c2876c9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -716,6 +716,11 @@ void GCNPassConfig::addMachineSSAOptimization() { addPass(&SIFoldOperandsID); addPass(&DeadMachineInstructionElimID); addPass(&SILoadStoreOptimizerID); + addPass(createSIShrinkInstructionsPass()); + if (EnableSDWAPeephole) { + addPass(&SIPeepholeSDWAID); + addPass(&DeadMachineInstructionElimID); + } } bool GCNPassConfig::addILPOpts() { @@ -757,11 +762,6 @@ bool GCNPassConfig::addGlobalInstructionSelect() { #endif void GCNPassConfig::addPreRegAlloc() { - addPass(createSIShrinkInstructionsPass()); - if (EnableSDWAPeephole) { - addPass(&SIPeepholeSDWAID); - addPass(&DeadMachineInstructionElimID); - } addPass(createSIWholeQuadModePass()); } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index 90c2cb914a3..c4a76de5989 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -amdgpu-sdwa-peephole=0 -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s +; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s ; CHECK-LABEL: {{^}}test_debug_value: ; CHECK: s_load_dwordx2 s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll index 1ced5da84e1..77d793201ad 100644 --- a/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s +; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s ; FIXME: we should disable sdwa peephole because dead-code elimination, that ; runs after peephole, ruins this test (different register numbers) |
