summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2010-05-11 00:04:31 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-11 00:04:31 +0000
commitb58b6f9a852da85f4f567dffa55f6818f72c9b94 (patch)
tree07cc656555f3f00e2aff8aa556f70b2818feffab
parent82bbfb58e3e301c3ff105d559393df5278929b36 (diff)
downloadbcm5719-llvm-b58b6f9a852da85f4f567dffa55f6818f72c9b94.tar.gz
bcm5719-llvm-b58b6f9a852da85f4f567dffa55f6818f72c9b94.zip
Ensure REG_SEQUENCE source operands are unique.
llvm-svn: 103449
-rw-r--r--llvm/lib/CodeGen/TwoAddressInstructionPass.cpp19
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 4ccb6611387..5b892a80e31 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1164,6 +1164,8 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
llvm_unreachable(0);
}
+
+ SmallSet<unsigned, 4> Seen;
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
unsigned SrcReg = MI->getOperand(i).getReg();
if (MI->getOperand(i).getSubReg() ||
@@ -1171,6 +1173,23 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
llvm_unreachable(0);
}
+
+ if (!Seen.insert(SrcReg)) {
+ // REG_SEQUENCE cannot have duplicated operands. Add a copy.
+ const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
+ unsigned NewReg = MRI->createVirtualRegister(RC);
+ bool Emitted =
+ TII->copyRegToReg(*MI->getParent(), MI, NewReg, SrcReg, RC, RC,
+ MI->getDebugLoc());
+ (void)Emitted;
+ assert(Emitted && "Unable to issue a copy instruction!\n");
+ MI->getOperand(i).setReg(NewReg);
+ MI->getOperand(i).setIsKill();
+ }
+ }
+
+ for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
+ unsigned SrcReg = MI->getOperand(i).getReg();
unsigned SrcIdx = MI->getOperand(i+1).getImm();
UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI);
}
OpenPOWER on IntegriCloud