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| author | Jim Grosbach <grosbach@apple.com> | 2010-07-09 20:27:06 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-07-09 20:27:06 +0000 |
| commit | 2a5725b1a324639d0e16e9c125f5713acfabca60 (patch) | |
| tree | c41993b6ab2aadf8f96460a5a8dc277afaa049fd | |
| parent | 4a5d086b50bcf6df6c2f2ddc69ed44d92582c728 (diff) | |
| download | bcm5719-llvm-2a5725b1a324639d0e16e9c125f5713acfabca60.tar.gz bcm5719-llvm-2a5725b1a324639d0e16e9c125f5713acfabca60.zip | |
In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327
llvm-svn: 108008
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/alloca.ll | 4 |
2 files changed, 12 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 8f22d177c2a..b9a9ecaac80 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -724,6 +724,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, SmallVector<unsigned, 4> UnspilledCS1GPRs; SmallVector<unsigned, 4> UnspilledCS2GPRs; ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); + MachineFrameInfo *MFI = MF.getFrameInfo(); // Spill R4 if Thumb2 function requires stack realignment - it will be used as // scratch register. @@ -820,9 +821,16 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // offset, make sure a register (or a spill slot) is available for the // register scavenger. Note that if we're indexing off the frame pointer, the // effective stack size is 4 bytes larger since the FP points to the stack - // slot of the previous FP. + // slot of the previous FP. Also, if we have variable sized objects in the + // function, stack slot references will often be negative, and some of + // our instructions are positive-offset only, so conservatively consider + // that case to want a spill slot (or register) as well. + // FIXME: We could add logic to be more precise about negative offsets + // and which instructions will need a scratch register for them. Is it + // worth the effort and added fragility? bool BigStack = RS && - estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF); + (estimateStackSize(MF) + (hasFP(MF) ? 4:0) >= estimateRSStackSizeLimit(MF)) + || MFI->hasVarSizedObjects(); bool ExtraCSSpill = false; if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { @@ -915,7 +923,6 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // note: Thumb1 functions spill to R12, not the stack. Reserve a slot // closest to SP or frame pointer. const TargetRegisterClass *RC = ARM::GPRRegisterClass; - MachineFrameInfo *MFI = MF.getFrameInfo(); RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false)); diff --git a/llvm/test/CodeGen/ARM/alloca.ll b/llvm/test/CodeGen/ARM/alloca.ll index 82a8c98599c..4a0835a2c0c 100644 --- a/llvm/test/CodeGen/ARM/alloca.ll +++ b/llvm/test/CodeGen/ARM/alloca.ll @@ -2,11 +2,11 @@ define void @f(i32 %a) { entry: -; CHECK: mov r11, sp +; CHECK: add r11, sp, #4 %tmp = alloca i8, i32 %a ; <i8*> [#uses=1] call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 ) ret void -; CHECK: mov sp, r11 +; CHECK: sub sp, r11, #4 } declare void @g(i8*, i32, i32, i32, i32) |

