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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-10 20:48:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-10 20:48:36 +0000 |
| commit | f42074b69995eda06e1ad2e5847673c5ebb70586 (patch) | |
| tree | fa313435790a3ca70b2be25d1c04091e632883b0 | |
| parent | d674e0ac0d36d74a91f4ce70e5bc50805c7d2c39 (diff) | |
| download | bcm5719-llvm-f42074b69995eda06e1ad2e5847673c5ebb70586.tar.gz bcm5719-llvm-f42074b69995eda06e1ad2e5847673c5ebb70586.zip | |
AMDGPU: Fix missing skipFunction calls
llvm-svn: 315361
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll | 2 |
3 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 46e58a2ca5f..4c991c7c21a 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -205,6 +205,9 @@ static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) { } bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(*MF.getFunction())) + return false; + const SISubtarget &ST = MF.getSubtarget<SISubtarget>(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); const SIInstrInfo *TII = ST.getInstrInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 24b7fe0f991..939062817a1 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -830,7 +830,7 @@ void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, const SISubtarget bool SIPeepholeSDWA::runOnMachineFunction(MachineFunction &MF) { const SISubtarget &ST = MF.getSubtarget<SISubtarget>(); - if (!ST.hasSDWA()) + if (!ST.hasSDWA() || skipFunction(*MF.getFunction())) return false; MRI = &MF.getRegInfo(); diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll index 269f582bccf..2122af62735 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll @@ -12,7 +12,7 @@ ; GCN-DAG: v_cmp_lt_i32 ; GCN-DAG: v_cmp_gt_i32 ; GCN: s_and_b64 -; GCN: s_and_saveexec_b64 +; GCN: s_mov_b64 exec ; GCN: s_or_b64 exec, exec ; GCN: v_cmp_eq_u32 |
