diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-30 00:45:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-30 00:45:18 +0000 |
| commit | e75b5e63a7bcbfb5c80e86447cb61a5afe541e86 (patch) | |
| tree | 34e88e41c0fbe7710ae19ab4b34959f3ce835681 | |
| parent | 61f7c3e843e940e2d664c0b573334aeebe292615 (diff) | |
| download | bcm5719-llvm-e75b5e63a7bcbfb5c80e86447cb61a5afe541e86.tar.gz bcm5719-llvm-e75b5e63a7bcbfb5c80e86447cb61a5afe541e86.zip | |
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 57bf66e9ef5..dad4c9fd2ec 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -111,6 +111,10 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && MVT::isFloatingPoint(Op.getOperand(2).getValueType())) { ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); + + // Cannot handle SETEQ/SETNE. + if (CC == ISD::SETEQ || CC == ISD::SETNE) break; + MVT::ValueType ResVT = Op.getValueType(); MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |

