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authorChris Lattner <sabre@nondot.org>2006-03-10 07:48:52 +0000
committerChris Lattner <sabre@nondot.org>2006-03-10 07:48:52 +0000
commitb87fbdbfd523eb89f6d67f53f5ed08fbce2eddb6 (patch)
tree2a66ac3071b5cbfea3f2df8ecb8f580a7a95b939
parenta5b93b8c6d45bf7195227ddae4db02147b45d272 (diff)
downloadbcm5719-llvm-b87fbdbfd523eb89f6d67f53f5ed08fbce2eddb6.tar.gz
bcm5719-llvm-b87fbdbfd523eb89f6d67f53f5ed08fbce2eddb6.zip
Simplify the interface to the schedulers, to not pass the selected heuristic
in. llvm-svn: 26691
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleDAG.h18
1 files changed, 4 insertions, 14 deletions
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 9c948a61f17..ba3637b5c32 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -34,16 +34,6 @@ namespace llvm {
typedef std::vector<NodeInfoPtr> NIVector;
typedef std::vector<NodeInfoPtr>::iterator NIIterator;
- // Scheduling heuristics
- enum SchedHeuristics {
- defaultScheduling, // Let the target specify its preference.
- noScheduling, // No scheduling, emit breadth first sequence.
- simpleScheduling, // Two pass, min. critical path, max. utilization.
- simpleNoItinScheduling, // Same as above exact using generic latency.
- listSchedulingBURR, // Bottom up reg reduction list scheduling.
- listSchedulingTD // Top-down list scheduler.
- };
-
/// HazardRecognizer - This determines whether or not an instruction can be
/// issued this cycle, and whether or not a noop needs to be inserted to handle
/// the hazard.
@@ -296,8 +286,7 @@ namespace llvm {
const TargetMachine &tm)
: DAG(dag), BB(bb), TM(tm) {}
- virtual ~ScheduleDAG() {
- };
+ virtual ~ScheduleDAG() {}
/// Run - perform scheduling.
///
@@ -337,10 +326,11 @@ namespace llvm {
std::map<SDNode*, unsigned> &VRBaseMap);
};
+ ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB);
+
/// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler.
- ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic,
- SelectionDAG &DAG,
+ ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG,
MachineBasicBlock *BB);
/// createBURRListDAGScheduler - This creates a bottom up register usage
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