Reland: [mips] Impose a threshold for coercion of aggregates

    Modified MipsABIInfo::classifyArgumentType so that it now coerces
    aggregate structures only if the size of said aggregate is less than
    16/64 bytes, depending on the ABI.

    Patch by Stefan Maksimovic.

    Differential Revision: https://reviews.llvm.org/D32900

with minor changes (use regexp instead of the hardcoded values) to the test.

llvm-svn: 302670

2 files changed, 46 insertions, 0 deletions

diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index 4ceb336d175..33d6a6ff414 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -6693,6 +6693,14 @@ MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
       return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
     }
 
+    // Use indirect if the aggregate cannot fit into registers for
+    // passing arguments according to the ABI
+    unsigned Threshold = IsO32 ? 16 : 64;
+
+    if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold))
+      return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+                                     getContext().getTypeAlign(Ty) / 8 > Align);
+
     // If we have reached here, aggregates are passed directly by coercing to
     // another structure type. Padding is inserted if the offset of the
     // aggregate is unaligned.
diff --git a/clang/test/CodeGen/mips-aggregate-arg.c b/clang/test/CodeGen/mips-aggregate-arg.c
new file mode 100644
index 00000000000..ccf30df7c22
--- /dev/null
+++ b/clang/test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+  char t1[10];
+};
+
+struct t2 {
+  char t2[20];
+};
+
+struct t3 {
+  char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32:  call void @f1(i32 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
+// O32:  call void @f2(%struct.t2* byval align 4 %{{.*}})
+// O32:  call void @f3(%struct.t3* byval align 4 %{{.*}})
+
+// N32-N64:  call void @f1(i64 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
+// N32-N64:  call void @f2(i64 inreg %{{[0-9]+}}, i64 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}})
+// N32-N64:  call void @f3(%struct.t3* byval align 8 %{{.*}})
+
+  f1(g1);
+  f2(g2);
+  f3(g3);
+}
+