Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-01-19T08:50:56+00:00 2019-01-19T08:50:56+00:00 Chandler Carruth chandlerc@gmail.com 2019-01-19T08:50:56+00:00 urn:sha1:2946cd701067404b99c39fb29dc9c74bd7193eb3 to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636 2018-11-30T14:15:13+00:00 Nicolai Haehnle nhaehnle@gmail.com 2018-11-30T14:15:13+00:00 urn:sha1:445b0b6260238f3e59204e6af921447564962004 Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992 2018-09-30T22:31:29+00:00 Fangrui Song maskray@google.com 2018-09-30T22:31:29+00:00 urn:sha1:3507c6e88479866e6b057ecbfd74b8d72b8275c3 There are a few leftovers in rL343163 which span two lines. This commit changes these llvm::sort(C.begin(), C.end, ...) to llvm::sort(C, ...) llvm-svn: 343426 2018-08-28T11:10:27+00:00 Simon Pilgrim llvm-dev@redking.me.uk 2018-08-28T11:10:27+00:00 urn:sha1:b7e10182cec42162e22bc483931be689b50371f4 Requested in post-commit review for rL339670 llvm-svn: 340819 2018-08-14T11:17:38+00:00 Simon Pilgrim llvm-dev@redking.me.uk 2018-08-14T11:17:38+00:00 urn:sha1:77af5fdb185e12c1e301a5fd28f99def0679f710 llvm-svn: 339670 2018-06-14T20:32:58+00:00 Florian Hahn florian.hahn@arm.com 2018-06-14T20:32:58+00:00 urn:sha1:6b1db82acf7785ed0b6c103b424402d25ee19891 llvm-svn: 334767 2018-06-14T20:23:48+00:00 Florian Hahn florian.hahn@arm.com 2018-06-14T20:23:48+00:00 urn:sha1:1b465767d6ca69f4b7201503f5f21e6125fe049a The return value of TreePatternNode::getChild is never null. This patch also updates various places that use return values of getChild to also use references. Those changes were suggested post-commit for D47463. llvm-svn: 334764 2018-05-29T18:34:42+00:00 Florian Hahn florian.hahn@arm.com 2018-05-29T18:34:42+00:00 urn:sha1:33b6f9acc4320ca244e383452273ebbef06904fc This should fix a few buildbot failures with old GCC versions. llvm-svn: 333448 2018-05-29T17:40:03+00:00 Florian Hahn florian.hahn@arm.com 2018-05-29T17:40:03+00:00 urn:sha1:7d3f9a88b963578e706f98558f3e3da431fdca56 Instead of dynamically allocating the vector for PhysRegs, we can allocate it on the stack and move it into InstructionMemo. Reviewers: mcrosier, craig.topper, RKSimon, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47461 llvm-svn: 333438 2018-05-22T14:36:58+00:00 Simon Dardis simon.dardis@mips.com 2018-05-22T14:36:58+00:00 urn:sha1:13de555737e07b29d126ed72d8450f88bd38f66c Some ISA's such as microMIPS32(R6) have instructions which are near identical for code generation purposes, e.g. xor and xor16. These instructions take the same value types for operands and return values, have the same instruction predicates and map to the same ISD opcode. (These instructions do differ by register classes.) In such cases, the FastISel generator rejects the instruction definition. This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables applying it to an instruction definition. Reviewers: mcrosier Differential Revision: https://reviews.llvm.org/D46953 llvm-svn: 332983