Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-10-11T20:58:26+00:00 2019-10-11T20:58:26+00:00 Quentin Colombet quentin.colombet@gmail.com 2019-10-11T20:58:26+00:00 urn:sha1:49036dd3aef9265270dcf4bb645050510b68e183 After r368065, all the tests using GISelMITest must call setUp() before doing anything, otherwise the TargetMachine is not going to be set up. A few tests added after that commit were not doing that and ended up testing effectively nothing. Fix the setup of all the tests and fix the failing tests. llvm-svn: 374595 2019-10-11T20:22:47+00:00 Quentin Colombet quentin.colombet@gmail.com 2019-10-11T20:22:47+00:00 urn:sha1:7720f1149867ac11543470a945438df59dcd2824 Teach buildMerge how to deal with scalar to vector kind of requests. Prior to this patch, buildMerge would issue either a G_MERGE_VALUES when all the vregs are scalars or a G_CONCAT_VECTORS when the destination vreg is a vector. G_CONCAT_VECTORS was actually not the proper instruction when the source vregs were scalars and the compiler would assert that the sources must be vectors. Instead we want is to issue a G_BUILD_VECTOR when we are in this situation. This patch fixes that. llvm-svn: 374588 2019-09-06T20:49:10+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-09-06T20:49:10+00:00 urn:sha1:cf10372119ca48ed0330d8225ca6165bf1dea801 llvm-svn: 371254 2019-08-06T17:18:29+00:00 Aditya Nandakumar aditya_nandakumar@apple.com 2019-08-06T17:18:29+00:00 urn:sha1:c8ac029d0ae27b8fd392f216d471ba2730be7fd1 https://reviews.llvm.org/D65698 This adds a KnownBits analysis pass for GISel. This was done as a pass (compared to static functions) so that we can add other features such as caching queries(within a pass and across passes) in the future. This patch only adds the basic pass boiler plate, and implements a lazy non caching knownbits implementation (ported from SelectionDAG). I've also hooked up the AArch64PreLegalizerCombiner pass to use this - there should be no compile time regression as the analysis is lazy. llvm-svn: 368065 2019-07-30T23:56:30+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-07-30T23:56:30+00:00 urn:sha1:9cf980d4a7ac7bda6f05807dd1e0456b8b2906ff llvm-svn: 367369 2019-06-24T15:50:29+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-06-24T15:50:29+00:00 urn:sha1:e3a676e9adba668a7da944766218e98dd4b2c10a Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191 2019-05-17T18:36:31+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-05-17T18:36:31+00:00 urn:sha1:f3cedf4823cedc2d073e1d278d1044198c049a7b Doesn't attempt to emit them for anything yet, but some legalizations I want to port use them. llvm-svn: 361061 2019-05-17T11:49:39+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-05-17T11:49:39+00:00 urn:sha1:e1a2a28d6bcd0ce80be06a69f2f1c7f9309847e8 llvm-svn: 361019 2019-05-17T11:49:35+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-05-17T11:49:35+00:00 urn:sha1:7f8ea15ffa193e0c5b8d0b20df335754ef038bcc Various expansions use these. llvm-svn: 361018 2019-05-16T13:04:20+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-05-16T13:04:20+00:00 urn:sha1:2120748f770d9cd6c5ea8fd6f051c5c1ad425756 llvm-svn: 360888