Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2020-05-02T03:42:53+00:00 2020-05-02T03:42:53+00:00 Fangrui Song maskray@google.com 2020-05-01T05:15:05+00:00 urn:sha1:d4d4c6bf834142326301a743d2939e868d9f0f0f After SHF_ALLOC sections are ordered by LMA: * If initial sections are empty, GNU objcopy skips their contents while we emit leading zeros. (binary-paddr.test %t4) * If trailing sections are empty, GNU objcopy skips their contents while we emit trailing zeros. (binary-paddr.test %t5) This patch matches GNU objcopy's behavior. Linkers don't keep p_memsz PT_LOAD segments. Such empty sections would not have a containing PT_LOAD and `Section::ParentSegment` might be null if linkers fail to optimize the file offsets (lld D79254). In particular, without D79254, the arm Linux kernel's multi_v5_defconfig depends on this behavior: in `vmlinux`, an empty .text_itcm is mapped at a very high address (0xfffe0000) but the kernel does not expect `objcopy -O binary` to create a very large `arch/arm/boot/Image` (0xfffe0000-0xc0000000 ~= 1GiB). See https://bugs.llvm.org/show_bug.cgi?id=45632 Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D79229 (cherry picked from commit ec786906f5feb4dceba1b5338927079e63e78095) 2020-04-12T05:20:59+00:00 Fangrui Song maskray@google.com 2020-03-22T06:39:01+00:00 urn:sha1:50d7e5d5e7db05b53d8832b49761eb627fd2eb63 Debian and some other distributions install llvm-strip as llvm-strip-$major (e.g. `/usr/bin/llvm-strip-9`) D54193 made it work with llvm-strip-$major but did not add a test. The behavior was regressed by D69146. Fixes https://github.com/ClangBuiltLinux/linux/issues/940 Reviewed By: alexshap Differential Revision: https://reviews.llvm.org/D76562 (cherry picked from commit f2f96eb605bc770e4da400dbcc7a6d2526ec1fd4) 2020-02-03T10:36:46+00:00 Hans Wennborg hans@chromium.org 2020-02-03T10:34:36+00:00 urn:sha1:e11d70cfe7e2a8537eb774ed1780e9ecd1aa90a0 (cherry picked from commit f00ab188f4e4214dfbecfdd8968a183e9363cefa) 2020-01-24T17:06:52+00:00 Fangrui Song maskray@google.com 2020-01-23T07:26:49+00:00 urn:sha1:425d15aeb13e2f60867654dd1abab515447a71ec Reviewed By: Bdragon28, jhenderson, grimar, sfertile Differential Revision: https://reviews.llvm.org/D73255 (cherry picked from commit f1dab29908d25a4044abff6ffc120c48b20f034d) 2020-01-15T11:19:00+00:00 Georgii Rymar grimar@accesssoftek.com 2020-01-15T11:16:03+00:00 urn:sha1:ca6f616532780b236556fc129cda3243d31cb01a This reverts commit 46d11e30ee807accefd14e0b7f306647963a39b5. It broke bots. E.g. http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/60744 2020-01-15T10:54:08+00:00 Georgii Rymar grimar@accesssoftek.com 2019-12-24T09:45:53+00:00 urn:sha1:46d11e30ee807accefd14e0b7f306647963a39b5 The encoded sequence of Elf*_Relr entries in a SHT_RELR section looks like [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] i.e. start with an address, followed by any number of bitmaps. The address entry encodes 1 relocation. The subsequent bitmap entries encode up to 63(31) relocations each, at subsequent offsets following the last address entry. More information is here: https://github.com/llvm-mirror/llvm/blob/master/lib/Object/ELF.cpp#L272 This patch adds a support for these sections. Differential revision: https://reviews.llvm.org/D71872 2020-01-14T14:09:12+00:00 Georgii Rymar grimar@accesssoftek.com 2019-12-26T11:55:53+00:00 urn:sha1:e1f524ea43f920767259c47e201405091d7e76fd This adds a few more tests for dynamic section. We only had tests for simple unknown values for 64-bits target, in this patch I've added OS specific and processor specific tags. Also it tests both 32 and 64-bits targets now. It will help to fix the formatting issues we have and diagnose a possible new ones. Differential revision: https://reviews.llvm.org/D71896 2020-01-14T11:47:19+00:00 Diogo Sampaio diogo.sampaio@arm.com 2020-01-13T11:36:02+00:00 urn:sha1:d94d079a6a5b12156e4b818c8ba46eb143f335b9 Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680 2020-01-14T09:51:52+00:00 Georgii Rymar grimar@accesssoftek.com 2020-01-14T09:51:52+00:00 urn:sha1:ec6579fc047f9ac18588b833dfde0b69064e013a This addresses post commit review comments for D71766. 2020-01-13T11:32:13+00:00 Miloš Stojanović Milos.Stojanovic@rt-rk.com 2019-12-25T10:23:01+00:00 urn:sha1:804dd6722762040e7ce7e04bf97b19d9596fee20 Add support for loading 32-bit immediates and enable the use of GPR64 registers. Differential Revision: https://reviews.llvm.org/D71873