Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2020-01-13T11:32:13+00:00 2020-01-13T11:32:13+00:00 Miloš Stojanović Milos.Stojanovic@rt-rk.com 2019-12-25T10:23:01+00:00 urn:sha1:804dd6722762040e7ce7e04bf97b19d9596fee20 Add support for loading 32-bit immediates and enable the use of GPR64 registers. Differential Revision: https://reviews.llvm.org/D71873 2019-12-18T09:21:06+00:00 Miloš Stojanović Milos.Stojanovic@rt-rk.com 2019-12-18T09:21:06+00:00 urn:sha1:862a60241687a2f718d2c4f554afd9d520da8952 Adding a basic lit test for MIPS. Differential Revision: https://reviews.llvm.org/D71605 2019-12-03T00:53:47+00:00 Wang, Pengfei pengfei.wang@intel.com 2019-11-27T13:09:17+00:00 urn:sha1:cf81714a7eb367260f9e6ae5f3bb11bb63d39124 Summary: Model MXCSR for AVX instructions other than AVX512 Reviewers: craig.topper, RKSimon Subscribers: hiraditya, llvm-commits, LuoYuanke, LiuChen3 Tags: #llvm Differential Revision: https://reviews.llvm.org/D70875 2019-12-02T15:13:27+00:00 Clement Courbet courbet@google.com 2019-12-02T13:58:41+00:00 urn:sha1:3540b80fe445ec467cba5e4cab2a4865bb945639 Summary: Add missing stack release instructions in loadImplicitRegAndFinalize. Reviewers: pengfei, gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70903 2019-12-02T12:18:35+00:00 Wang, Pengfei pengfei.wang@intel.com 2019-12-02T11:39:16+00:00 urn:sha1:76b70f6f75e90074bf2f5168383cc3afc21b61ad Summary: This is a following up to D70874. It adds the initialization of FPCW in llvm-exegesis. Reviewers: craig.topper, RKSimon, courbet, gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70891 2019-12-02T10:19:32+00:00 Wang, Pengfei pengfei.wang@intel.com 2019-12-01T05:35:53+00:00 urn:sha1:44b9942898c7167ed95cccef4c3da3d2113e11e8 Summary: This patch is used to initialize the new added register MXCSR. Reviewers: craig.topper, RKSimon Subscribers: tschuett, courbet, llvm-commits, LiuChen3 Tags: #llvm Differential Revision: https://reviews.llvm.org/D70874 2019-10-11T11:33:18+00:00 Clement Courbet courbet@google.com 2019-10-11T11:33:18+00:00 urn:sha1:c8eb0547efc568ac688010961a5c19934caad4a2 Reviewers: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68780 llvm-svn: 374533 2019-10-09T08:49:13+00:00 Clement Courbet courbet@google.com 2019-10-09T08:49:13+00:00 urn:sha1:c3a7fb7599316d57bc197fe566bf2bd3b65cb330 Summary: This will help for PR32326. This shows the well-known issue with `RBP` and `R13` as base registers. Reviewers: gchatelet Subscribers: tschuett, llvm-commits, RKSimon, andreadb Tags: #llvm Differential Revision: https://reviews.llvm.org/D68646 llvm-svn: 374146 2019-10-08T14:30:24+00:00 Clement Courbet courbet@google.com 2019-10-08T14:30:24+00:00 urn:sha1:2cd0f2895946de546d066f67c88ff365d3210017 Summary: This adds a `-max-configs-per-opcode` option to limit the number of configs per opcode. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68642 llvm-svn: 374054 2019-10-08T09:06:48+00:00 Clement Courbet courbet@google.com 2019-10-08T09:06:48+00:00 urn:sha1:4919534ae4d4029982d5a5ad7ea18f4a681cb602 Summary: Right now there are no snippet generators that emit the `Config` Field, but I plan to add it to investigate LEA operands for PR32326. What was broken was: - `Config` Was not propagated up until the BenchmarkResult::Key. - Clustering should really consider different configs as measuring different things, so we should stabilize on (Opcode, Config) instead of just Opcode. Reviewers: gchatelet Subscribers: tschuett, llvm-commits, lebedev.ri Tags: #llvm Differential Revision: https://reviews.llvm.org/D68629 llvm-svn: 374031