bcm5719-llvm/llvm/test/Transforms/SLPVectorizer/AMDGPU, branch meklort-10.0.1

[LAA] Re-check bit-width of pointers after stripping.

2019-07-18T17:30:27+00:00

Summary: - As the pointer stripping now tracks through `addrspacecast`, prepare to handle the bit-width difference from the result pointer. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64928 llvm-svn: 366470

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17T09:51:07+00:00

llvm-svn: 363538

Revert "Temporarily Revert "Add basic loop fusion pass.""

2019-04-17T04:52:47+00:00

The reversion apparently deleted the test/Transforms directory. Will be re-reverting again. llvm-svn: 358552

Temporarily Revert "Add basic loop fusion pass."

2019-04-17T02:12:23+00:00

As it's causing some bot failures (and per request from kbarton). This reverts commit r358543/ab70da07286e618016e78247e4a24fcb84077fda. llvm-svn: 358546

Fix vectorization of canonicalize

2018-09-17T13:24:30+00:00

llvm-svn: 342390

SLPVectorizer: Fix assert with different sized address spaces

2018-08-31T14:34:53+00:00

llvm-svn: 341215

[SLP] Recognize min/max pattern using instructions producing same values.

2018-07-02T17:55:31+00:00

Summary: It is common to have the following min/max pattern during the intermediate stages of SLP since we only optimize at the end. This patch tries to catch such patterns and allow more vectorization. %1 = extractelement <2 x i32> %a, i32 0 %2 = extractelement <2 x i32> %a, i32 1 %cond = icmp sgt i32 %1, %2 %3 = extractelement <2 x i32> %a, i32 0 %4 = extractelement <2 x i32> %a, i32 1 %select = select i1 %cond, i32 %3, i32 %4 Author: FarhanaAleen Reviewed By: ABataev, RKSimon, spatel Differential Revision: https://reviews.llvm.org/D47608 llvm-svn: 336130

[SLP] Add testcases of min/max reduction pattern for AMDGPU.

2018-06-11T20:29:31+00:00

Author: FarhanaAleen llvm-svn: 334435

AMDGPU: Make v2i16/v2f16 legal on VI

2018-05-22T06:32:10+00:00

This usually results in better code. Fixes using inline asm with short2, and also fixes having a different ABI for function parameters between VI and gfx9. Partially cleans up the mess used for lowering of the d16 operations. Making v4f16 legal will help clean this up more, but this requires additional work. llvm-svn: 332953

[AMDGPU] Support horizontal vectorization of min/max.

2018-05-09T21:18:34+00:00

Author: FarhanaAleen Reviewed By: rampitec Subscribers: AMDGPU Differential Revision: https://reviews.llvm.org/D46604 llvm-svn: 331920