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<title>bcm5719-llvm/llvm/test/Transforms/LoopUnroll/ARM, branch meklort-10.0.1</title>
<subtitle>Project Ortega BCM5719 LLVM</subtitle>
<id>https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1</id>
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<updated>2020-01-10T09:41:41+00:00</updated>
<entry>
<title>Follow up of 67bf9a6154d4b82c, minor fix in test case, removed duplicate option</title>
<updated>2020-01-10T09:41:41+00:00</updated>
<author>
<name>Sjoerd Meijer</name>
<email>sjoerd.meijer@arm.com</email>
</author>
<published>2020-01-10T09:41:41+00:00</published>
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<id>urn:sha1:356685a1d8972180f472c1333e8e89dbcc704c1d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[SVEV] Recognise hardware-loop intrinsic loop.decrement.reg</title>
<updated>2020-01-10T09:35:00+00:00</updated>
<author>
<name>Sjoerd Meijer</name>
<email>sjoerd.meijer@arm.com</email>
</author>
<published>2020-01-10T09:30:02+00:00</published>
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<id>urn:sha1:67bf9a6154d4b82c6c01aad01141bf08c1bbd0f6</id>
<content type='text'>
Teach SCEV about the @loop.decrement.reg intrinsic, which has exactly the same
semantics as a sub expression. This allows us to query hardware-loops, which
contain this @loop.decrement.reg intrinsic, so that we can calculate iteration
counts, exit values, etc. of hardwareloops.

This "int_loop_decrement_reg" intrinsic is defined as "IntrNoDuplicate". Thus,
while hardware-loops and tripcounts now become analysable by SCEV, this
prevents the usual loop transformations from applying transformations on
hardware-loops, which is what we want at this point, for which I have added
test cases for loopunrolling and IndVarSimplify and LFTR.

Differential Revision: https://reviews.llvm.org/D71563
</content>
</entry>
<entry>
<title>[ARM][MVE] Don't unroll intrinsic loops.</title>
<updated>2020-01-09T11:57:34+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2020-01-09T11:57:04+00:00</published>
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<id>urn:sha1:15c7fa4d11eeb50095ae571c645427b9a267bdee</id>
<content type='text'>
We don't unroll vector loops for MVE targets, but we miss the case
when loops only contain intrinsic calls. So just move the logic a
bit to catch this case.

Differential Revision: https://reviews.llvm.org/D72440
</content>
</entry>
<entry>
<title>[MVE] Don't try to unroll vectorised MVE loops</title>
<updated>2019-08-11T08:53:18+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2019-08-11T08:53:18+00:00</published>
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<id>urn:sha1:11c4602fce16c22858de764bff21be4160d323af</id>
<content type='text'>
Due to the nature of the beat system in the MVE architecture, along with tail
predication and low-overhead loops, unrolling has less benefit compared to
normal loops. You can not, for example, hide the latency of a load with other
instructions as you can for scalar code. Preventing unrolling also makes the
code easier to read and reason about.

So if a loop contains vector code, don't enable the runtime unrolling. At least
for the time being.

Differential Revision: https://reviews.llvm.org/D65803

llvm-svn: 368530
</content>
</entry>
<entry>
<title>[lit] Delete empty lines at the end of lit.local.cfg NFC</title>
<updated>2019-06-17T09:51:07+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>maskray@google.com</email>
</author>
<published>2019-06-17T09:51:07+00:00</published>
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<id>urn:sha1:ac14f7b10cffe2be548607269e036244cd16acc3</id>
<content type='text'>
llvm-svn: 363538
</content>
</entry>
<entry>
<title>[ARM] Enable Unroll UpperBound</title>
<updated>2019-06-10T10:22:14+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2019-06-10T10:22:14+00:00</published>
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<id>urn:sha1:d847aa573b655fe71aad323c7f579c6302c702aa</id>
<content type='text'>
This option allows loops with small max trip counts to be fully unrolled. This
can help with code like the remainder loops from manually unrolled loops like
those that appear in the cmsis dsp library. We would apparently previously
runtime unroll them with the default unroll count (4).

Differential Revision: https://reviews.llvm.org/D63064

llvm-svn: 362928
</content>
</entry>
<entry>
<title>Revert "Temporarily Revert "Add basic loop fusion pass.""</title>
<updated>2019-04-17T04:52:47+00:00</updated>
<author>
<name>Eric Christopher</name>
<email>echristo@gmail.com</email>
</author>
<published>2019-04-17T04:52:47+00:00</published>
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<id>urn:sha1:cee313d288a4faf0355d76fb6e0e927e211d08a5</id>
<content type='text'>
The reversion apparently deleted the test/Transforms directory.

Will be re-reverting again.

llvm-svn: 358552
</content>
</entry>
<entry>
<title>Temporarily Revert "Add basic loop fusion pass."</title>
<updated>2019-04-17T02:12:23+00:00</updated>
<author>
<name>Eric Christopher</name>
<email>echristo@gmail.com</email>
</author>
<published>2019-04-17T02:12:23+00:00</published>
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<id>urn:sha1:a86343512845c9c1fdbac865fea88aa5fce7142a</id>
<content type='text'>
As it's causing some bot failures (and per request from kbarton).

This reverts commit r358543/ab70da07286e618016e78247e4a24fcb84077fda.

llvm-svn: 358546
</content>
</entry>
<entry>
<title>[ARM] Use Cortex-A57 sched model for Cortex-A72</title>
<updated>2018-10-25T15:08:29+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2018-10-25T15:08:29+00:00</published>
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<id>urn:sha1:a16667e79be9164943dd76235d5406ae519b9042</id>
<content type='text'>
This mirrors what we already do for AArch64 as the cores are similar.
As discussed in the review, enabling the machine scheduler causes
more variations in performance changes so it is not enabled for now.
This patch improves LNT scores by a geomean of 1.57% at -O3.

Differential Revision: https://reviews.llvm.org/D53562

llvm-svn: 345272
</content>
</entry>
<entry>
<title>[ARM] Allow unrolling of multi-block loops.</title>
<updated>2017-10-23T08:05:14+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2017-10-23T08:05:14+00:00</published>
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<id>urn:sha1:487ab869422b1eb7be932eb70445d9d0541fdce1</id>
<content type='text'>
Before, loop unrolling was only enabled for loops with a single
block. This restriction has been removed and replaced by:
- allow a maximum of two exiting blocks,
- a four basic block limit for cores with a branch predictor.

Differential Revision: https://reviews.llvm.org/D38952

llvm-svn: 316313
</content>
</entry>
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