bcm5719-llvm/llvm/test/MC/Mips/mips64r6, branch meklort-10.0.1Project Ortega BCM5719 LLVMhttps://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.12019-10-03T12:08:26+00:00[mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions2019-10-03T12:08:26+00:00Simon Atanasyansimon@atanasyan.com2019-10-03T12:08:26+00:00urn:sha1:f6551ddfceb676d2fb09e509ed39051c003927db
llvm-svn: 373591
[mips] Support sigrie instruction2018-11-06T14:37:24+00:00Simon Atanasyansimon@atanasyan.com2018-11-06T14:37:24+00:00urn:sha1:bb36aea1d5c9fb4ae3870dec5ba3f8aa41d6a9dc
The `sigrie` instruction signals a Reserved Instruction Exception.
This patch adds support for assembling / disassembling the instruction.
Differential Revision: http://reviews.llvm.org/D53861
llvm-svn: 346230
[mips] Add missing instructions2018-08-29T11:35:03+00:00Aleksandar Beserminjiabeserminji@wavecomp.com2018-08-29T11:35:03+00:00urn:sha1:f8f00e5065f728be233a7c644245c2611a008968
Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.
Differential Revision: https://reviews.llvm.org/D50437
llvm-svn: 340920
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions2018-06-01T16:37:53+00:00Simon Atanasyansimon@atanasyan.com2018-06-01T16:37:53+00:00urn:sha1:e80c3ce9cc100b0960c23380163aacbedd191996
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.
The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.
Differential Revision: https://reviews.llvm.org/D47316
llvm-svn: 333774
[mips] Fix the predicates of round, ceiling, floor and trunc.2018-05-14T16:26:50+00:00Simon Dardissimon.dardis@mips.com2018-05-14T16:26:50+00:00urn:sha1:bb818b4421233ff122c7aa254095ff9f5f119e64
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46691
llvm-svn: 332258
[mips] Accept 32-bit offsets for ld/sd/lld commands2018-05-10T16:01:36+00:00Simon Atanasyansimon@atanasyan.com2018-05-10T16:01:36+00:00urn:sha1:05db279f528435890314d11737d706719269c8be
This is a follow up to the rL330983. The patch teaches ld, sd, and lld
commands accept 32-bit memory offsets by replacing `mem_simm16` operand
to `mem_simmptr`. In fact, these commands should accept 64-bit offsets,
but so large offsets require another command expanding and will be
supported by a separate patch.
Differential Revision: https://reviews.llvm.org/D46629
llvm-svn: 331997
[mips] Accept 32-bit offsets for lh and lhu commands2018-05-10T16:01:18+00:00Simon Atanasyansimon@atanasyan.com2018-05-10T16:01:18+00:00urn:sha1:ac5f4e0546fb2a333d14c7cf7ce69a01c123e002
This is a follow up to the rL330983. The patch teaches lh and lhu
commands accepts 32-bit memory offsets by replacing `mem_simm16` operand
to `mem_simmptr`.
Differential Revision: https://reviews.llvm.org/D46513
llvm-svn: 331996
[mips] Correct the predicates of sign extension instructions2018-05-04T15:00:54+00:00Simon Dardissimon.dardis@mips.com2018-05-04T15:00:54+00:00urn:sha1:65b0492f0daa23a655c591d6f23fab9a911f6af2
And eliminatw the duplication of those instructions for microMIPS32r6.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46117
llvm-svn: 331526
Revert "[mips] Correct the predicates of sign extension instructions"2018-05-02T12:35:29+00:00Simon Dardissimon.dardis@mips.com2018-05-02T12:35:29+00:00urn:sha1:694fde215e59f8f5854ae6f2251330175f26c8fd
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.
This reverts r331346.
llvm-svn: 331348
[mips] Correct the predicates of sign extension instructions2018-05-02T12:25:33+00:00Simon Dardissimon.dardis@mips.com2018-05-02T12:25:33+00:00urn:sha1:7a36495bf74a411d52c6dcf5b4db459fec21f89e
And eliminate the duplication of those instructions for microMIPS32r6.
llvm-svn: 331346