bcm5719-llvm/llvm/test/MC/Mips/mips3, branch meklort-10.0.1 Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2018-08-29T11:35:03+00:00 [mips] Add missing instructions 2018-08-29T11:35:03+00:00 Aleksandar Beserminji abeserminji@wavecomp.com 2018-08-29T11:35:03+00:00 urn:sha1:f8f00e5065f728be233a7c644245c2611a008968 Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920 [mips] Correct predicates for loads, bit manipulation instructions and some pseudos 2018-06-20T19:59:58+00:00 Simon Dardis simon.dardis@mips.com 2018-06-20T19:59:58+00:00 urn:sha1:6021424c102621097302215b8be4b49d5abbda08 Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162 [mips] Fix the predicates of round, ceiling, floor and trunc. 2018-05-14T16:26:50+00:00 Simon Dardis simon.dardis@mips.com 2018-05-14T16:26:50+00:00 urn:sha1:bb818b4421233ff122c7aa254095ff9f5f119e64 Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258 [mips] Correct the predicates of cvt.fmt.fmt instructions 2018-05-10T10:42:30+00:00 Simon Dardis simon.dardis@mips.com 2018-05-10T10:42:30+00:00 urn:sha1:ce6ada41513eeff22e04b52d7965cdf02d8fe6fe Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969 [mips] Correct the predicates for shifts. 2018-05-02T09:55:49+00:00 Simon Dardis simon.dardis@mips.com 2018-05-02T09:55:49+00:00 urn:sha1:6cfc9ba5e3ea2dba7c0bbb2e26dc6653568c7d8e Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341 Reland "[mips] Guard traps for microMIPS correctly" 2018-04-24T17:11:37+00:00 Simon Dardis simon.dardis@mips.com 2018-04-24T17:11:37+00:00 urn:sha1:d2ac0faf3bdcdc3629b7447f009d98face285ba0 This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741 [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. 2018-04-12T12:37:02+00:00 Simon Dardis simon.dardis@mips.com 2018-04-12T12:37:02+00:00 urn:sha1:a5a3c38c3d1044933c2a928a084b8fee48ba63fc Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905 Revert "[mips] Guard traps for microMIPS correctly" 2018-03-13T17:31:11+00:00 Simon Dardis simon.dardis@mips.com 2018-03-13T17:31:11+00:00 urn:sha1:e5f72dd5e1b14814c1fbb0a10cbf02222782e5bd This appears to have broken the expensive checks bot in a strange fashion. Reverting until I can investigate. This reverts r327409. llvm-svn: 327427 [mips] Guard traps for microMIPS correctly 2018-03-13T15:46:58+00:00 Simon Dardis simon.dardis@mips.com 2018-03-13T15:46:58+00:00 urn:sha1:d5ae61d49d5bb8f8af07fee043dfc0da4cdd3137 This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 llvm-svn: 327409 [mips] Correct the definition of m(f|t)c(0|2) 2018-03-07T11:39:48+00:00 Simon Dardis simon.dardis@mips.com 2018-03-07T11:39:48+00:00 urn:sha1:52ae4f078e0c14e51ef4e7f8734b935c8a7aebd2 These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890