bcm5719-llvm/llvm/test/MC/Mips/mips1, branch meklort-10.0.1 Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-06-12T17:52:05+00:00 [Mips] Add s.d instruction alias for Mips1 2019-06-12T17:52:05+00:00 Simon Atanasyan simon@atanasyan.com 2019-06-12T17:52:05+00:00 urn:sha1:efc0d1a29801adc95450b9a2129f213d15c23164 Add support for s.d instruction for Mips1 which expands into two swc1 instructions. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D63199 llvm-svn: 363184 [mips] Add missing instructions 2018-08-29T11:35:03+00:00 Aleksandar Beserminji abeserminji@wavecomp.com 2018-08-29T11:35:03+00:00 urn:sha1:f8f00e5065f728be233a7c644245c2611a008968 Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920 [mips] Correct predicates for loads, bit manipulation instructions and some pseudos 2018-06-20T19:59:58+00:00 Simon Dardis simon.dardis@mips.com 2018-06-20T19:59:58+00:00 urn:sha1:6021424c102621097302215b8be4b49d5abbda08 Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162 [mips] Guard some floating point instructions correctly 2018-06-12T10:28:06+00:00 Simon Dardis simon.dardis@mips.com 2018-06-12T10:28:06+00:00 urn:sha1:74fb5e678982ea7e09da5dc19866ff24979d1e20 Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47636 llvm-svn: 334491 [mips] Correct the predicates for shifts. 2018-05-02T09:55:49+00:00 Simon Dardis simon.dardis@mips.com 2018-05-02T09:55:49+00:00 urn:sha1:6cfc9ba5e3ea2dba7c0bbb2e26dc6653568c7d8e Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341 [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. 2018-04-12T12:37:02+00:00 Simon Dardis simon.dardis@mips.com 2018-04-12T12:37:02+00:00 urn:sha1:a5a3c38c3d1044933c2a928a084b8fee48ba63fc Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905 [mips] Correct the definition of m(f|t)c(0|2) 2018-03-07T11:39:48+00:00 Simon Dardis simon.dardis@mips.com 2018-03-07T11:39:48+00:00 urn:sha1:52ae4f078e0c14e51ef4e7f8734b935c8a7aebd2 These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890 Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. 2018-02-09T02:13:15+00:00 Douglas Yung douglas.yung@sony.com 2018-02-09T02:13:15+00:00 urn:sha1:6562b3d954b57b04daf0b1bf72c402d9aabd633e llvm-svn: 324699 [mips] Define certain instructions in microMIPS32r3 2018-02-08T09:25:17+00:00 Stefan Maksimovic stefan.maksimovic@mips.com 2018-02-08T09:25:17+00:00 urn:sha1:b3e7ed3b941b3477b7797860eb99cb5154ba015e Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584 [mips] Properly select abs and sqrt instructions 2018-01-23T10:09:39+00:00 Stefan Maksimovic stefan.maksimovic@mips.com 2018-01-23T10:09:39+00:00 urn:sha1:98749e0249892886dcbdf1c972b762660dc09029 - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184