Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2017-11-14T22:26:42+00:00 2017-11-14T22:26:42+00:00 Simon Dardis simon.dardis@mips.com 2017-11-14T22:26:42+00:00 urn:sha1:de5ed0c58e4471e51f46d0572142788aaebb0143 This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207 2017-08-14T16:20:33+00:00 Simon Dardis simon.dardis@imgtec.com 2017-08-14T16:20:33+00:00 urn:sha1:c3f6b2806f2a73e3b98d6c2e3aa36b0e8795eef7 This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854 2017-08-14T12:28:00+00:00 Simon Dardis simon.dardis@imgtec.com 2017-08-14T12:28:00+00:00 urn:sha1:cbf55deaa17a378155db9d2fea141c81fe78521b This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834 2017-07-14T15:08:05+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-14T15:08:05+00:00 urn:sha1:45b2277a33251927be13f96b066ca638b25b3184 FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030 2017-07-14T13:44:12+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-14T13:44:12+00:00 urn:sha1:b3529841db7de92eab80a4b6aee88170343e4dd4 Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023 2017-07-13T19:27:41+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-13T19:27:41+00:00 urn:sha1:1558ee3365111f84af2b73d18c76ca17f25539c3 This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939 2017-07-12T19:47:45+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-12T19:47:45+00:00 urn:sha1:e171a913d62bdc8a5434d0d1915fabb6e907fc6a Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836 2017-07-12T16:23:57+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-12T16:23:57+00:00 urn:sha1:76eb647e1eaa6120e068d21e79606426d20622b9 Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808 2017-07-12T14:48:27+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-12T14:48:27+00:00 urn:sha1:2de1ddbd9c592c5297c6f02e52a472af2ed2ea3c Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793 2017-07-12T12:33:40+00:00 Simon Dardis simon.dardis@imgtec.com 2017-07-12T12:33:40+00:00 urn:sha1:7323f7ac636d118b621deefd21324a1c052af976 llvm-svn: 307779