bcm5719-llvm/llvm/test/MC/Disassembler/Mips/mips32r3, branch meklort-10.0.1 Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2018-08-29T11:35:03+00:00 [mips] Add missing instructions 2018-08-29T11:35:03+00:00 Aleksandar Beserminji abeserminji@wavecomp.com 2018-08-29T11:35:03+00:00 urn:sha1:f8f00e5065f728be233a7c644245c2611a008968 Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920 [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. 2018-04-12T12:37:02+00:00 Simon Dardis simon.dardis@mips.com 2018-04-12T12:37:02+00:00 urn:sha1:a5a3c38c3d1044933c2a928a084b8fee48ba63fc Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905 [mips] Define certain instructions in microMIPS32r3 2018-02-08T09:25:17+00:00 Stefan Maksimovic stefan.maksimovic@mips.com 2018-02-08T09:25:17+00:00 urn:sha1:b3e7ed3b941b3477b7797860eb99cb5154ba015e Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584 [mips] Properly select abs and sqrt instructions 2018-01-23T10:09:39+00:00 Stefan Maksimovic stefan.maksimovic@mips.com 2018-01-23T10:09:39+00:00 urn:sha1:98749e0249892886dcbdf1c972b762660dc09029 - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184 [mips] Place certain 64 bit FPU instructions in their own decoder namespace 2017-10-05T10:27:37+00:00 Simon Dardis simon.dardis@imgtec.com 2017-10-05T10:27:37+00:00 urn:sha1:51a7ae2a2936dd686115950871cb599cf47cf089 Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976 Recommit: "[mips] Add rsqrt, recip for MIPS" 2016-10-05T16:11:01+00:00 Simon Dardis simon.dardis@imgtec.com 2016-10-05T16:11:01+00:00 urn:sha1:f45a59f80b213c2a23d9b022b56c8f347a901fe5 Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334 Revert "[mips] Add rsqrt, recip for MIPS" 2016-10-05T15:28:33+00:00 Simon Dardis simon.dardis@imgtec.com 2016-10-05T15:28:33+00:00 urn:sha1:bbfd5287489fe2a55d71097c6e4914ace20d7d7f This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327 [mips] Add rsqrt, recip for MIPS 2016-09-27T12:25:15+00:00 Simon Dardis simon.dardis@imgtec.com 2016-09-27T12:25:15+00:00 urn:sha1:0486d585c59a993e5d2dfffe18b487e1886ac853 Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485 [mips] Range check uimm16 and fix several bugs this revealed. 2016-02-01T15:13:31+00:00 Daniel Sanders daniel.sanders@imgtec.com 2016-02-01T15:13:31+00:00 urn:sha1:f8bb23e50923e550de71af44ead47cf37b486deb Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360 [mips] Add missing MIPS32 - MIPS32R5 disassembler tests. 2015-09-11T15:28:19+00:00 Daniel Sanders daniel.sanders@imgtec.com 2015-09-11T15:28:19+00:00 urn:sha1:9676db005e6cfc7e724a12365bb320e85422d1ba llvm-svn: 247420