Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2020-02-05T12:53:24+00:00 2020-02-05T12:53:24+00:00 David Green david.green@arm.com 2020-02-04T09:25:01+00:00 urn:sha1:8195a96595baca8c0141de2a121dcf3f8c0ea616 Under MVE, we do not have any lowering for fminimum, which a vector_reduce_fmin without NoNan will be expanded into. As with the other recent patches, force this to expand in the pre-isel pass. Note that Neon lowering would be OK because the scalar fminimum uses the vector VMIN instruction, but is probably better to just rely on the scalar operations, which is what is done here. Also fixes what appears to be the reversal of INF vs -INF in the vector_reduce_fmin widening code. (cherry picked from commit 362d00e0510ee75750499e2993a782428e377215) 2020-01-15T08:10:38+00:00 David Green david.green@arm.com 2020-01-15T07:50:14+00:00 urn:sha1:1b264a8263f8656bd9c09c471af9b43422429ef6 The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test. 2020-01-14T16:10:55+00:00 Sjoerd Meijer sjoerd.meijer@arm.com 2020-01-14T16:00:59+00:00 urn:sha1:a08c0adee072226179736c4f6caf3dd0b7a7c9af Fix a missing and broken test: 2 VPT blocks predicated on the same VCMP instruction that can be folded. The problem was that for each VPT block, we record the predicate statements with a list, but the same instruction was added twice. Thus, we were running in an assert trying to remove the same instruction twice. To avoid this the instructions are now recorded with a set. Differential Revision: https://reviews.llvm.org/D72699 2020-01-14T12:03:58+00:00 Sam Parker sam.parker@arm.com 2020-01-14T12:02:32+00:00 urn:sha1:e27632c3026328e41b0d7dbf25631041e979a2f9 We have a whitelist of instructions that we allow when tail predicating, since these are trivial ones that we've deemed need no special handling. Now change ARMLowOverheadLoops to allow the non-trivial instructions if they're contained within a valid VPT block. Since a valid block is one that is predicated upon the VCTP so we know that these non-trivial instructions will still behave as expected once the implicit predication is used instead. This also fixes a previous test failure. Differential Revision: https://reviews.llvm.org/D72509 2020-01-14T11:47:34+00:00 Sam Parker sam.parker@arm.com 2020-01-10T14:47:29+00:00 urn:sha1:bad6032bc15fa8d16b67b86ef2b2fe48724e756e Use the already provided helper function to get the operand type so that we can detect whether the vpr is being used as a predicate or not. Also use existing helpers to get the predicate indices when we converting the vpt blocks. This enables us to support both types of vpr predicate operand. Differential Revision: https://reviews.llvm.org/D72504 2020-01-14T11:47:19+00:00 Diogo Sampaio diogo.sampaio@arm.com 2020-01-13T11:36:02+00:00 urn:sha1:d94d079a6a5b12156e4b818c8ba46eb143f335b9 Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680 2020-01-14T11:41:17+00:00 Sam Parker sam.parker@arm.com 2020-01-14T11:02:32+00:00 urn:sha1:e73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7 Due to the current way that we collect predicated instructions, we can't easily handle vpsel in tail predicated loops. There are a couple of issues: 1) It will use the VPR as a predicate operand, but doesn't have to be instead a VPT block, which means we can assert while building up the VPT block because we don't find another VPST to being a new one. 2) VPSEL still requires a VPR operand even after tail predicating, which means we can't remove it unless there is another instruction, such as vcmp, that can provide the VPR def. The first issue should be a relatively simple fix in the logic of the LowOverheadLoops pass, whereas the second will require us to represent the 'implicit' tail predication with an explicit value. Differential Revision: https://reviews.llvm.org/D72629 2020-01-14T10:33:52+00:00 Anna Welker anna.welker@arm.com 2020-01-14T09:48:02+00:00 urn:sha1:72ca86fd34ecc5f7ccbaf923d2d508dad2a6a64c Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330 2020-01-10T19:00:17+00:00 Craig Topper craig.topper@intel.com 2020-01-10T18:31:25+00:00 urn:sha1:b590e0fd810e4caf59ab83b04654d42e18faaafb ONE is currently softened to OGT | OLT. But the libcalls for OGT and OLT libcalls will trigger an exception for QNAN. At least for X86 with libgcc. UEQ on the other hand uses UO | OEQ. The UO and OEQ libcalls will not trigger an exception for QNAN. This patch changes ONE to use the inverse of the UEQ lowering. So we now produce O & UNE. Technically the existing behavior was correct for a signalling ONE, but since I don't know how to generate one of those from clang that seemed like something we can deal with later as we would need to fix other predicates as well. Also removing spurious exceptions seemed better than missing an exception. There are also problems with quiet OGT/OLT/OLE/OGE, but those are harder to fix. Differential Revision: https://reviews.llvm.org/D72477 2020-01-10T13:40:41+00:00 Diogo Sampaio diogo.sampaio@arm.com 2020-01-10T13:32:02+00:00 urn:sha1:b1bb5ce96d349689085eab38121c85737de1fcaa Summary: This reverts commit 8c12769f3046029e2a9b4e48e1645b1a77d28650. Reviewers: Subscribers: