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<title>bcm5719-llvm/llvm/test/CodeGen/Mips, branch meklort-10.0.1</title>
<subtitle>Project Ortega BCM5719 LLVM</subtitle>
<id>https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1</id>
<link rel='self' href='https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1'/>
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<updated>2020-01-13T14:14:03+00:00</updated>
<entry>
<title>[MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols</title>
<updated>2020-01-13T14:14:03+00:00</updated>
<author>
<name>Alex Richardson</name>
<email>Alexander.Richardson@cl.cam.ac.uk</email>
</author>
<published>2020-01-13T13:52:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=8e8ccf4712cf58562a91c197da3efd4f9963ce0d'/>
<id>urn:sha1:8e8ccf4712cf58562a91c197da3efd4f9963ce0d</id>
<content type='text'>
The R_(MICRO)MIPS_JALR optimization only works when used against functions.
Using the relocation against a data symbol (e.g. function pointer) will
cause some linkers that don't ignore the hint in this case (e.g. LLD prior
to commit 5bab291b7b) to generate a relative branch to the data symbol
which crashes at run time. Before this patch, LLVM was erroneously emitting
these relocations against local-dynamic TLS function pointers and global
function pointers with internal visibility.

Reviewers: atanasyan, jrtc27, vstefanovic
Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D72571
</content>
</entry>
<entry>
<title>[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)</title>
<updated>2020-01-13T11:08:12+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2020-01-13T11:07:53+00:00</published>
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<id>urn:sha1:8f49204f26ea8856b870d4c2344b98f4b706bea0</id>
<content type='text'>
As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.

Differential Revision: https://reviews.llvm.org/D72573
</content>
</entry>
<entry>
<title>[MIPS] Regenerate shl/lshr shift tests</title>
<updated>2020-01-12T14:35:34+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2020-01-12T14:35:34+00:00</published>
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<id>urn:sha1:a888277897f75b2952d96de229fff57519cfc363</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructions</title>
<updated>2020-01-09T20:46:02+00:00</updated>
<author>
<name>Alex Richardson</name>
<email>Alexander.Richardson@cl.cam.ac.uk</email>
</author>
<published>2020-01-07T12:31:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=646ca7d7e72e8408b3fa3472018eb9d1c2643ff5'/>
<id>urn:sha1:646ca7d7e72e8408b3fa3472018eb9d1c2643ff5</id>
<content type='text'>
Summary:
In commit b91f239485fb7bb8d29be3e0b60660a2de7570a9 I updated the
MipsDelaySlotFiller to skip BUNDLE instructions.
However, in addition to not considering BUNDLE instructions for the delay
slot, we also need to ensure that the register def-use information is
updated. Not updating this information caused run-time crashes (when using
the out-of-tree CHERI backend) since later definitions could be overwritten
with earlier register values.

Reviewers: atanasyan
Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D72254
</content>
</entry>
<entry>
<title>GlobalISel: Correct result type for G_FCMP in lowerFPTOUI</title>
<updated>2020-01-06T22:21:51+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-01-04T22:06:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=1060b9e23b8f9d2802835896947ec281ba3b4f6b'/>
<id>urn:sha1:1060b9e23b8f9d2802835896947ec281ba3b4f6b</id>
<content type='text'>
Using the final result type doesn't make any sense. Use the natural
default boolean type for the select condition.
</content>
</entry>
<entry>
<title>[MIPS GlobalISel] Select bitreverse. Recommit</title>
<updated>2019-12-30T17:06:29+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@rt-rk.com</email>
</author>
<published>2019-12-30T17:06:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=98f72a5107ce781a8ec93c524c3fdb08c241f0e5'/>
<id>urn:sha1:98f72a5107ce781a8ec93c524c3fdb08c241f0e5</id>
<content type='text'>
G_BITREVERSE is generated from llvm.bitreverse.&lt;type&gt; intrinsics,
clang genrates these intrinsics from __builtin_bitreverse32 and
__builtin_bitreverse64.
Add lower and narrowscalar for G_BITREVERSE.
Lower G_BITREVERSE on MIPS32.

Recommit notes:
Introduce temporary variables in order to make sure
instructions get inserted into MachineFunction in same order
regardless of compiler used to build llvm.

Differential Revision: https://reviews.llvm.org/D71363
</content>
</entry>
<entry>
<title>Revert "[MIPS GlobalISel] Select bitreverse"</title>
<updated>2019-12-30T13:29:47+00:00</updated>
<author>
<name>Dmitri Gribenko</name>
<email>gribozavr@gmail.com</email>
</author>
<published>2019-12-30T13:28:56+00:00</published>
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<id>urn:sha1:32cc14100e802fddd9f88e7a862250ce3108a583</id>
<content type='text'>
This reverts commit dbc136e0fe7e14c64dcb78e72321bb41af60afa4.
It broke buildbots:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21066
</content>
</entry>
<entry>
<title>[MIPS GlobalISel] Select bitreverse</title>
<updated>2019-12-30T10:26:45+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@rt-rk.com</email>
</author>
<published>2019-12-30T10:26:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=dbc136e0fe7e14c64dcb78e72321bb41af60afa4'/>
<id>urn:sha1:dbc136e0fe7e14c64dcb78e72321bb41af60afa4</id>
<content type='text'>
G_BITREVERSE is generated from llvm.bitreverse.&lt;type&gt; intrinsics,
clang genrates these intrinsics from __builtin_bitreverse32 and
__builtin_bitreverse64.
Add lower and narrowscalar for G_BITREVERSE.
Lower G_BITREVERSE on MIPS32.

Differential Revision: https://reviews.llvm.org/D71363
</content>
</entry>
<entry>
<title>[MIPS GlobalISel] Select bswap</title>
<updated>2019-12-30T10:13:22+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@rt-rk.com</email>
</author>
<published>2019-12-30T10:13:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=94a24e7a401be7a3db0ddfa2035855b75c8cc55d'/>
<id>urn:sha1:94a24e7a401be7a3db0ddfa2035855b75c8cc55d</id>
<content type='text'>
G_BSWAP is generated from llvm.bswap.&lt;type&gt; intrinsics, clang genrates
these intrinsics from __builtin_bswap32 and __builtin_bswap64.
Add lower and narrowscalar for G_BSWAP.
Lower G_BSWAP on MIPS32, select G_BSWAP on MIPS32 revision 2 and later.

Differential Revision: https://reviews.llvm.org/D71362
</content>
</entry>
<entry>
<title>Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351</title>
<updated>2019-12-25T00:27:51+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>maskray@google.com</email>
</author>
<published>2019-12-25T00:11:33+00:00</published>
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<id>urn:sha1:a36ddf0aa9db5c1086e04f56b5f077b761712eb5</id>
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</content>
</entry>
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