Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-09-11T11:16:48+00:00 2019-09-11T11:16:48+00:00 Guillaume Chatelet gchatelet@google.com 2019-09-11T11:16:48+00:00 urn:sha1:48904e9452de81375bd55d830d08e51cc8f2ec7e Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608 2019-06-19T00:25:39+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-06-19T00:25:39+00:00 urn:sha1:9cac4e6d1403554b06ec2fc9d834087b1234b695 This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757 2018-01-31T22:04:26+00:00 Puyan Lotfi puyan@puyan.org 2018-01-31T22:04:26+00:00 urn:sha1:43e94b15ea0c180ebb0fd3e6b697dac4564aaf60 Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922 2017-12-18T15:56:40+00:00 Simon Dardis simon.dardis@mips.com 2017-12-18T15:56:40+00:00 urn:sha1:fd8c65e868ae2bc59475a14fa328c133dcbd84a0 Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. This version has the correct commit message. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41183 llvm-svn: 320991 2017-12-18T12:30:34+00:00 Simon Dardis simon.dardis@mips.com 2017-12-18T12:30:34+00:00 urn:sha1:f70af977af43380e760f7c722ec089ae10e86208 This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975 2017-12-18T12:24:17+00:00 Simon Dardis simon.dardis@mips.com 2017-12-18T12:24:17+00:00 urn:sha1:c3c0d4590bb6cf3444e3cf0cf6ea138d3478b670 Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. Reviewers: atanasyan https://reviews.llvm.org/D41183 llvm-svn: 320974 2017-09-14T10:58:00+00:00 Simon Dardis simon.dardis@imgtec.com 2017-09-14T10:58:00+00:00 urn:sha1:28365b33adf531c67f5b03f1293b5dd58f51256b This patch complements D16810 "[mips] Make isel select the correct DEXT variant up front.". Now ISel picks the right variant of DINS, so now there is no need to replace DINS with the appropriate variant during MipsMCCodeEmitter::encodeInstruction(). This patch also enables target specific instruction verification for ins, dins, dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these constraints are not checked during instruction selection. Adding machine verification should catch outstanding cases. Finally, correct a bug that instruction verification uncovered, where the position operand of a DINSU generated during lowering was being silently and accidently corrected to the correct value. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34809 llvm-svn: 313254