Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-12-25T00:27:51+00:00 2019-12-25T00:27:51+00:00 Fangrui Song maskray@google.com 2019-12-25T00:11:33+00:00 urn:sha1:a36ddf0aa9db5c1086e04f56b5f077b761712eb5 2019-12-24T23:57:33+00:00 Fangrui Song maskray@google.com 2019-12-24T23:52:21+00:00 urn:sha1:502a77f125f43ffde57af34d3fd1b900248a91cd 2019-11-13T08:23:08+00:00 joanlluch joan.lluch@icloud.com 2019-11-13T08:23:08+00:00 urn:sha1:d384ad6b636d4a8c55ef53d5316d008a05161b1f Summary: Replaces ``` unsigned getShiftAmountThreshold(EVT VT) ``` by ``` bool shouldAvoidTransformToShift(EVT VT, unsigned amount) ``` thus giving more flexibility for targets to decide whether particular shift amounts must be considered expensive or not. Updates the MSP430 target with a custom implementation. This continues D69116, D69120, D69326 and updates them, so all of them must be committed before this. Existing tests apply, a few more have been added. Reviewers: asl, spatel Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70042 2019-11-11T15:15:33+00:00 joanlluch joan.lluch@icloud.com 2019-11-11T15:15:33+00:00 urn:sha1:abbbf9880c272da7a3db5de40a91dcbddac8bb50 Summary: Baseline tests before applying D70042 Reviewers: spatel, asl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70083 2019-11-11T09:18:25+00:00 joanlluch joan.lluch@icloud.com 2019-11-11T09:17:57+00:00 urn:sha1:e0012c5d6acb568c77c7a6b845637f330e64515f Summary: Additional filtering of undesired shifts for targets that do not support them efficiently. Related with D69116 and D69120 Applies the TLI.getShiftAmountThreshold hook to prevent undesired generation of shifts for the following IR code: ``` define i16 @testShiftBits(i16 %a) { entry: %and = and i16 %a, -64 %cmp = icmp eq i16 %and, 64 %conv = zext i1 %cmp to i16 ret i16 %conv } define i16 @testShiftBits_11(i16 %a) { entry: %cmp = icmp ugt i16 %a, 63 %conv = zext i1 %cmp to i16 ret i16 %conv } define i16 @testShiftBits_12(i16 %a) { entry: %cmp = icmp ult i16 %a, 64 %conv = zext i1 %cmp to i16 ret i16 %conv } ``` The attached diff file shows the piece code in TargetLowering that is responsible for the generation of shifts in relation to the IR above. Before applying this patch, shifts will be generated to replace non-legal icmp immediates. However, shifts may be undesired if they are even more expensive for the target. For all my previous patches in this series (cited above) I added test cases for the MSP430 target. However, in this case, the target is not suitable for showing improvements related with this patch, because the MSP430 does not implement "isLegalICmpImmediate". The default implementation returns always true, therefore the patched code in TargetLowering is never reached for that target. Targets implementing both "isLegalICmpImmediate" and "getShiftAmountThreshold" will benefit from this. The differential effect of this patch can only be shown for the MSP430 by temporarily implementing "isLegalICmpImmediate" to return false for large immediates. This is simulated with the implementation of a command line flag that was incorporated in D69975 This patch belongs to a initiative to "relax" the generation of shifts by LLVM for targets requiring it Reviewers: spatel, lebedev.ri, asl Reviewed By: spatel Subscribers: lenary, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69326 2019-11-08T22:16:44+00:00 joanlluch joan.lluch@icloud.com 2019-11-08T22:16:44+00:00 urn:sha1:fe0763d28a572f72007637c7bd097bc19cbb58fc Summary: This is baseline tests for D69326 Incorporates a command line flag for the MSP430 and adds a test cases to help showing the effects of applying D69326 More details and motivation for this patch in D69326 Reviewers: spatel, asl, lebedev.ri Reviewed By: spatel, asl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69975 2019-11-04T18:41:41+00:00 Sanjay Patel spatel@rotateright.com 2019-11-04T18:41:41+00:00 urn:sha1:113181e9bd05353ed562ee7b971bf7f1e58cd5de Continuation of: D69116 Contributes to a fix for PR43559: https://bugs.llvm.org/show_bug.cgi?id=43559 See also D69099 and D69116 Use the TLI hook in DAGCombine.cpp to guard against creating shift nodes that are not optimal for a target. Patch by: @joanlluch (Joan LLuch) Differential Revision: https://reviews.llvm.org/D69120 2019-10-30T18:15:25+00:00 Sanjay Patel spatel@rotateright.com 2019-10-30T18:15:25+00:00 urn:sha1:3e85571432514c7c16a11640a366059d57d8dd0d 2019-10-30T18:12:58+00:00 Sanjay Patel spatel@rotateright.com 2019-10-30T18:11:55+00:00 urn:sha1:67da730da636ec64e93c0ce850d086a78016c9ad Baseline results for D69120. Patch by: @joanlluch (Joan LLuch) 2019-10-19T16:57:02+00:00 Sanjay Patel spatel@rotateright.com 2019-10-19T16:57:02+00:00 urn:sha1:a298964d22a203d21bafe1f649a46ba8a2592ca4 Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling codegen improvements on targets with no multiple shift instructions and cheap selects or branches. Contributes to a Fix for PR43559: https://bugs.llvm.org/show_bug.cgi?id=43559 Patch by: @joanlluch (Joan LLuch) Differential Revision: https://reviews.llvm.org/D69116 llvm-svn: 375347