bcm5719-llvm/llvm/test/CodeGen/AVR, branch meklort-10.0.1

[AVR] Fix codegen for rotate instructions

2019-12-23T03:41:28+00:00

Summary: This patch introduces the ROLBRd and RORBRd pseudo-instructions, which implemenent the "traditional" rotate operations; instead of the AVR rotate instructions that use the carry bit. The code is not optimized at all. Especially when dealing with loops of rotate instructions, this codegen should be improved some day. Related bug: 41358 //Note//: This is my first submitted patch. Reviewers: dylanmckay, Jim Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits, dylanmckay, dsprenkels Tags: #llvm Patched by dsprenkels (Daan Sprenkels) Differential Revision: https://reviews.llvm.org/D60365

[AVR] Fix tests after r363757

2019-07-04T06:12:47+00:00

r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in select-must-add-unconditional-jump.mir needed updating to refer to finalize-isel. llvm-svn: 365108

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17T09:51:07+00:00

llvm-svn: 363538

[AVR] Fix the 'avr-tiny.ll' and 'avr25.ll' subtarget feature tests

2019-06-12T08:31:07+00:00

When these tests were originally written, the middle end would introduce an unnecessary copy from r24:r23->GPR16->r24:r23, and these tests mistakenly relied on it. The most optimal codegen for the functions in the test cases before this patch would be NOPs. This is because the first i16 argument always gets the same register allocation as an i16 return value in the AVR calling convention. These tests broke in r362963 when the codegen was improved and the redundant copy was eliminated. After this, the test functions were lowered to their optimal form - a 'ret' and nothing else. This patch prepends an extra i16 operand to each of the test functions so that a 16-bit copy must be inserted for the program to be correct. llvm-svn: 363131

[AVR] Fix the 'load.ll' test after r362351

2019-06-06T08:06:50+00:00

In that commit, the 'load.ll' test was modified, but still failed. This commit updates the test so that it now passes. llvm-svn: 362684

[AVR] Fix incorrect source regclass of LDWRdPtr

2019-06-03T02:31:07+00:00

Summary: LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z. So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: dylanmckay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62300 llvm-svn: 362351

[AVR] Disable register coalescing to the PTRDISPREGS class

2019-06-01T12:38:56+00:00

If we would allow register coalescing on PTRDISPREGS class then register allocator can lock Z register to some virtual register. Larger instructions requiring a memory acces then fail during the register allocation phase since there is no available register to hold a pointer if Y register was already taken for a stack frame. This patch prevents it by keeping Z register spillable. It does it by not allowing coalescer to lock it. Original discussion on https://github.com/avr-rust/rust/issues/128. llvm-svn: 362298

Add TargetLoweringInfo hook for explicitly setting the ABI calling convention endianess

2019-05-21T06:38:02+00:00

Summary: The endianess used in the calling convention does not always match the endianess of the target on all architectures, namely AVR. When an argument is too large to be legalised by the architecture and is split for the ABI, a new hook TargetLoweringInfo::shouldSplitFunctionArgumentsAsLittleEndian is queried to find the endianess that function arguments must be laid out in. This approach was recommended by Eli Friedman. Originally reported in https://github.com/avr-rust/rust/issues/129. Patch by Carl Peto. Reviewers: bogner, t.p.northover, RKSimon, niravd, efriedma Reviewed By: efriedma Subscribers: JDevlieghere, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62003 llvm-svn: 361222

[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

2019-03-13T17:07:09+00:00

Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068

[AVR] Insert unconditional branch when inserting MBBs between blocks with fallthrough

2019-01-21T04:32:02+00:00

This updates the AVR Select8/Select16 expansion code so that, when inserting the two basic blocks for true and false conditions, any existing fallthrough on the previous block is preserved. Prior to this patch, if the block before the Select pseudo fell through to the subsequent block, two new basic blocks would be inserted at the prior fallthrough point, changing the fallthrough destination. The predecessor or successor lists were not updated, causing the BranchFolding pass at -O1 and above the rearrange basic blocks, causing an infinite loop. Not to mention the unconditional fallthrough to the true block is incorrect in of itself. This patch modifies the Select8/16 expansion so that, if inserting true and false basic blocks at a fallthrough point, the implicit branch is preserved by means of an explicit, unconditional branch to the previous fallthrough destination. Thanks to Carl Peto for reporting this bug. This fixes avr-rust bug https://github.com/avr-rust/rust/issues/123. llvm-svn: 351721