Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=ortega-7.0.1 2018-09-10T08:11:26+00:00 2018-09-10T08:11:26+00:00 Hans Wennborg hans@hanshq.net 2018-09-10T08:11:26+00:00 urn:sha1:3472e2a5a51ff45ddf7a62dec3ce7a0451f04fa3 ------------------------------------------------------------------------ r341642 | tnorthover | 2018-09-07 11:21:25 +0200 (Fri, 07 Sep 2018) | 8 lines ARM: fix Thumb2 CodeGen for ldrex with folded frame-index. Because t2LDREX (& t2STREX) were marked as AddrModeNone, but did allow a FrameIndex operand, rewriteT2FrameIndex asserted. This gives them a proper addressing-mode and tells the rewriter about it so that encodable offsets are exploited and others are rejected. Should fix PR38828. ------------------------------------------------------------------------ llvm-svn: 341783 2018-08-13T08:03:40+00:00 Hans Wennborg hans@hanshq.net 2018-08-13T08:03:40+00:00 urn:sha1:de814ae68121720d3fa63b32b8e52e95f667be98 ------------------------------------------------------------------------ r339225 | thopre | 2018-08-08 11:35:26 +0200 (Wed, 08 Aug 2018) | 11 lines Support inline asm with multiple 64bit output in 32bit GPR Summary: Extend fix for PR34170 to support inline assembly with multiple output operands that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR as in the PR). Reviewers: bogner, t.p.northover, lattner, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, tra, eraman, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45437 ------------------------------------------------------------------------ llvm-svn: 339539 2018-07-31T23:09:42+00:00 Reid Kleckner rnk@google.com 2018-07-31T23:09:42+00:00 urn:sha1:b32ff46ff7159469a583c1a0bc6e48cf7bab4361 Disable ARMCodeGenPrepare by default again. It is causing verifier failues in V8 that look like: Duplicate integer as switch case switch i32 %trunc, label %if.end13 [ i32 0, label %cleanup36 i32 0, label %if.then8 ], !dbg !4981 i32 0 fatal error: error in backend: Broken function found, compilation aborted! I will continue reducing the test case and send it along. llvm-svn: 338452 2018-07-31T09:04:14+00:00 Sam Parker sam.parker@arm.com 2018-07-31T09:04:14+00:00 urn:sha1:2a6c842fda75c31152d9a2617ebcdfd1a0533a83 Re-enabling ARMCodeGenPrepare by default after failing to reproduce the bootstrap issues that I was concerned it was causing. llvm-svn: 338354 2018-07-30T16:48:39+00:00 Thomas Preud'homme thomas.preudhomme@arm.com 2018-07-30T16:48:39+00:00 urn:sha1:196149c943ffde9f2f3368fc47d5f843a9ab44a4 This reapplies commit r338206 reverted by r338214 since the bug that r338206 uncovered has been fixed in r338268. Add support for inline assembly with matching input operand that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR). Note that regular input is already handled by existing code. llvm-svn: 338269 2018-07-30T16:45:40+00:00 Thomas Preud'homme thomas.preudhomme@arm.com 2018-07-30T16:45:40+00:00 urn:sha1:6c1b0752997a8bf0c3109bcf4101eff24d97c9ce Summary: Fix read of uninitialized RC variable in ARM's PrintAsmOperand when hasRegClassConstraint returns false. This was causing inline-asm-operand-implicit-cast test to fail in r338206. Reviewers: t.p.northover, weimingz, javed.absar, chill Reviewed By: chill Subscribers: chill, eraman, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D49984 llvm-svn: 338268 2018-07-30T08:49:30+00:00 Petr Pavlu petr.pavlu@arm.com 2018-07-30T08:49:30+00:00 urn:sha1:8b6eff4e77f07f2afd738a97a821b5d292b9fdf1 Code in `CC_ARM_AAPCS_Custom_Aggregate()` is responsible for handling homogeneous aggregates for `CC_ARM_AAPCS_VFP`. When an aggregate ends up fully on stack, the function tries to pack all resulting items of the aggregate as tightly as possible according to AAPCS. Once the first item was laid out, the alignment used for consecutive items was the size of one item. This logic went wrong for 128-bit vectors because their alignment is normally only 64 bits, and so could result in inserting unexpected padding between the first and second element. The patch fixes the problem by updating the alignment with the item size only if this results in reducing it. Differential Revision: https://reviews.llvm.org/D49720 llvm-svn: 338233 2018-07-29T14:30:49+00:00 Sanjay Patel spatel@rotateright.com 2018-07-29T14:30:49+00:00 urn:sha1:7312206f2f3c8fe69d52d7a7c31292cfa0949735 Example of bot failure: http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5107/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Ainline-asm-operand-implicit-cast.ll llvm-svn: 338214 2018-07-28T21:33:39+00:00 Thomas Preud'homme thomas.preudhomme@arm.com 2018-07-28T21:33:39+00:00 urn:sha1:74ffd14e15f4a3ed5110637e1bb3cfb9399ec057 Add support for inline assembly with matching input operand that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR). Note that regular input is already handled by existing code. llvm-svn: 338206 2018-07-28T00:27:25+00:00 Craig Topper craig.topper@intel.com 2018-07-28T00:27:25+00:00 urn:sha1:50b1d4303d0e710007bc2ebc895a378e53204400 This can be useful since addition is commutable, and subtraction is not. This matches a transform that is also done by InstCombine. llvm-svn: 338181