Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-10-16T09:37:03+00:00 2019-10-16T09:37:03+00:00 Sam Parker sam.parker@arm.com 2019-10-16T09:37:03+00:00 urn:sha1:1c3ca61294de428c93639a35afac725b7cbb1ffb Instead of inserting everything after the 'root' of the reduction, insert all instructions as close to their operands as possible. This can help reduce register pressure. Differential Revision: https://reviews.llvm.org/D67392 llvm-svn: 374981 2019-10-11T08:36:54+00:00 QingShan Zhang qshanz@cn.ibm.com 2019-10-11T08:36:54+00:00 urn:sha1:bb8d54001075ed22fc63d366e33c3fcdfa3fd3e0 Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like: llvm::MCSchedClassDesc ModelASchedClasses[] = { ... InstA, 0, ... InstB, -1,... }; llvm::MCSchedClassDesc ModelBSchedClasses[] = { ... InstA, -1,... InstB, 0,... }; The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now: llvm::MCSchedClassDesc ModelASchedClasses[] = { ... InstA, 0, ... InstB, 0,... }; llvm::MCSchedClassDesc ModelBSchedClasses[] = { ... InstA, 0,... InstB, 0,... }; And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB. Differential Revision: https://reviews.llvm.org/D67950 llvm-svn: 374524 2019-09-29T08:38:48+00:00 David Green david.green@arm.com 2019-09-29T08:38:48+00:00 urn:sha1:120a5e9a745f931d805d63c6c5313a1aa24d98f5 This is an attempt to fill in some of the missing instructions from the Cortex-M4 schedule, and make it easier to do the same for other ARM cpus. - Some instructions are marked as hasNoSchedulingInfo as they are pseudos or otherwise do not require scheduling info - A lot of features have been marked not supported - Some WriteRes's have been added for cvt instructions. - Some extra instruction latencies have been added, notably by relaxing the regex for dsp instruction to catch more cases, and some fp instructions. This goes a long way to get the CompleteModel working for this CPU. It does not go far enough as to get all scheduling info for all output operands correct. Differential Revision: https://reviews.llvm.org/D67957 llvm-svn: 373163 2019-09-11T08:17:48+00:00 Sam Parker sam.parker@arm.com 2019-09-11T08:17:48+00:00 urn:sha1:17ea9b463c66a6a9e978e87b9363c24e8e7e6e42 Add test for ParallelDSP. llvm-svn: 371594 2019-09-09T08:39:14+00:00 Sam Parker sam.parker@arm.com 2019-09-09T08:39:14+00:00 urn:sha1:c363deb575019c6cb28a6d1c92826e36ea8bb07c The incoming accumulator value can be discovered through a sext, in which case there will be a mismatch between the input and the result. So sign extend the accumulator input if we're performing a 64-bit mac. Differential Revision: https://reviews.llvm.org/D67220 llvm-svn: 371370 2019-09-04T08:41:34+00:00 Sam Parker sam.parker@arm.com 2019-09-04T08:41:34+00:00 urn:sha1:fea532230bf4cf677d0ae6028eedf0135aa8b9e2 For any unpaired muls, we accumulate them as an input to the reduction. Check the type of the mul and perform a sext if the existing accumlator input type is not the same. Differential Revision: https://reviews.llvm.org/D66993 llvm-svn: 370851 2019-08-28T08:51:13+00:00 Sam Parker sam.parker@arm.com 2019-08-28T08:51:13+00:00 urn:sha1:a761ba0f2d4bb4e977a3cef52d569e34e721f8bc rL369567 reverted a couple of recent changes made to ARMParallelDSP because of a miscompilation error: PR43073. The issue stemmed from an underlying bug that was caused by adding muls into a reduction before it was proved that they could be executed in parallel with another mul. Most of the changes here are from the previously reverted commits. The additional changes have been made area: 1) The Search function now doesn't insert any muls into the Reduction object. That now happens once the search has successfully finished. 2) For any muls added into the reduction but that weren't paired, we accumulate their values as an input into the smlad. Differential Revision: https://reviews.llvm.org/D66660 llvm-svn: 370171 2019-08-21T19:53:42+00:00 Nico Weber nicolasweber@gmx.de 2019-08-21T19:53:42+00:00 urn:sha1:ed18e70c86f6de353cebe0a8faa961a341c74d27 llvm-svn: 369567 2019-08-09T07:48:50+00:00 Sam Parker sam.parker@arm.com 2019-08-09T07:48:50+00:00 urn:sha1:0dba791a25e7e520760e0c5127434a0377bc50db As loads are combined and widened, we replaced their sext users operands whereas we should have been replacing the uses of the sext. I've added a load of tests, with only a few of them originally causing assertion failures, the rest improve pattern coverage. Differential Revision: https://reviews.llvm.org/D65740 llvm-svn: 368404 2019-07-31T07:32:03+00:00 Sam Parker sam.parker@arm.com 2019-07-31T07:32:03+00:00 urn:sha1:2200a9bdf351914d8d8c68cea966a9aec50ec0fd Run across a whole function, visiting each basic block one at a time. Differential Revision: https://reviews.llvm.org/D65324 llvm-svn: 367389