Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2020-02-03T15:00:00+00:00 2020-02-03T15:00:00+00:00 Nicolai Hähnle nicolai.haehnle@amd.com 2020-01-21T08:17:25+00:00 urn:sha1:94c79ce5740f69aa9a9f5145c9911a61b7d20662 This reverts commit 0dc6c249bffac9f23a605ce4e42a84341da3ddbd. The commit is reported to cause a regression in piglit/bin/glsl-vs-loop for Mesa. (cherry picked from commit a80291ce10ba9667352adcc895f9668144f5f616) 2020-01-15T09:48:16+00:00 cdevadas cdevadas@amd.com 2020-01-10T16:53:27+00:00 urn:sha1:0dc6c249bffac9f23a605ce4e42a84341da3ddbd The current implementation of skip insertion (SIInsertSkip) makes it a mandatory pass required for correctness. Initially, the idea was to have an optional pass. This patch inserts the s_cbranch_execz upfront during SILowerControlFlow to skip over the sections of code when no lanes are active. Later, SIRemoveShortExecBranches removes the skips for short branches, unless there is a sideeffect and the skip branch is really necessary. This new pass will replace the handling of skip insertion in the existing SIInsertSkip Pass. Differential revision: https://reviews.llvm.org/D68092 2020-01-13T18:09:38+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-05T19:26:53+00:00 urn:sha1:203801425d222555fa2617fff19ecd861525429f 2020-01-13T17:51:05+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-03T15:07:01+00:00 urn:sha1:2f090cc8f1a3144c81b024bdc52ec1ae49dc0def A future change will try to fold constant offsets into the loop which these will stress. 2020-01-13T17:51:05+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-06T03:09:24+00:00 urn:sha1:ca19d7a3993c69633826ae388155c9ad176b11df The branch target needs to be changed depending on whether there is an unconditional branch or not. Loops also need to be similarly fixed, but compiling a simple testcase end to end requires another set of patches that aren't upstream yet. 2020-01-13T13:29:45+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-10T22:50:45+00:00 urn:sha1:d7d88b9d8b3efd8b4b07074aa64b5b4136a35b2c It's possible to have a type that needs a mask greater than 64-bits. 2020-01-13T03:44:51+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-12T22:10:18+00:00 urn:sha1:555e7ee04cb5c44e0b11a2eda999e6910b4b27e1 We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG> 2020-01-13T03:44:51+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-13T00:12:59+00:00 urn:sha1:a10527cd3731e2ef246c4797fb099385a948f62f getDefIgnoringCopies will fail to find any def if no type is set if we try to use it on the use's operand, so propagate the type. 2020-01-10T14:42:49+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-10T14:06:47+00:00 urn:sha1:bac995d97896c1e785d709da24c55f0e050eb899 Also clamps G_SEXT/G_ANYEXT, but the implementation is more limited so fewer cases actually work. 2020-01-10T00:52:24+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2020-01-02T21:45:33+00:00 urn:sha1:35c3d101aee240f6c034f25ff6800fda22a89987 Doesn't try to do the fold into the base register of an add of a constant in the index like the DAG path does.