bcm5719-llvm/llvm/lib/Target/X86/InstPrinter, branch meklort-10.0.1Project Ortega BCM5719 LLVMhttps://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.12019-05-10T23:24:38+00:00[X86] Move InstPrinter files to MCTargetDesc. NFC2019-05-10T23:24:38+00:00Richard Trieurtrieu@google.com2019-05-10T23:24:38+00:00urn:sha1:b28b8b7724ef03cadae3e6ac8eda3f6be7f7ffe6
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
llvm-svn: 360484
[X86] Fix uninitialized members in constructor warnings. NFCI.2019-05-06T14:48:02+00:00Simon Pilgrimllvm-dev@redking.me.uk2019-05-06T14:48:02+00:00urn:sha1:2a0ef0530beec95e29198d311348c65717acdc2b
Initialize all member variables in X86ATTInstPrinter and X86DAGToDAGISel constructors to fix cppcheck warning.
llvm-svn: 360047
[X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.2019-04-05T19:27:41+00:00Craig Toppercraig.topper@intel.com2019-04-05T19:27:41+00:00urn:sha1:e0bfeb5f24979416144c16e8b99204f5f163b889
Summary:
Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models.
This avoids needing an isel pattern for each condition code. And it removes
translation switches for converting between CMOV instructions and condition
codes.
Now the printer, encoder and disassembler take care of converting the immediate.
We use InstAliases to handle the assembly matching. But we print using the
asm string in the instruction definition. The instruction itself is marked
IsCodeGenOnly=1 to hide it from the assembly parser.
This does complicate the scheduler models a little since we can't assign the
A and BE instructions to a separate class now.
I plan to make similar changes for SETcc and Jcc.
Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet
Reviewed By: RKSimon
Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60041
llvm-svn: 357800
[X86] Remove the _alt forms of (V)CMP instructions. Use a combination of custom printing and custom parsing to achieve the same result and more2019-03-18T17:59:59+00:00Craig Toppercraig.topper@intel.com2019-03-18T17:59:59+00:00urn:sha1:c2b35ebc1da58c4095d48743c65e6d9d5968a621
Similar to previous change done for VPCOM and VPCMP
Differential Revision: https://reviews.llvm.org/D59468
llvm-svn: 356384
[X86] Hopefully fix a tautological compare warning in printVecCompareInstr.2019-03-18T07:05:01+00:00Craig Toppercraig.topper@intel.com2019-03-18T07:05:01+00:00urn:sha1:ba898da132d4b4f6eeb5211e94cd141458383eee
llvm-svn: 356359
[X86] Add tab character to the custom printing of VPCMP and VPCOM instructions.2019-03-18T02:53:11+00:00Craig Toppercraig.topper@intel.com2019-03-18T02:53:11+00:00urn:sha1:860a27208ecd2e4770750a3a68570a528f8b9057
All the other instructions are printed with a preceeding tab.
llvm-svn: 356355
[X86] Merge printf32mem/printi32mem into a single printdwordmem. Do the same for all other printing functions.2019-03-17T22:57:21+00:00Craig Toppercraig.topper@intel.com2019-03-17T22:57:21+00:00urn:sha1:04cc28fe1330b43f21294134f4243771221a7943
The only thing the print methods currently need to know is the string to print for the memory size in intel syntax.
This patch merges the functions based on this string. If we ever need something else in the future, its easy to split them back out.
This reduces the number of cases in the assembly printers. It shrinks the intel printer to only use 7 bytes per instruction instead of 8.
llvm-svn: 356352
[X86] Remove the _alt forms of AVX512 VPCMP instructions. Use a combination of custom printing and custom parsing to achieve the same result and more2019-03-17T21:21:40+00:00Craig Toppercraig.topper@intel.com2019-03-17T21:21:40+00:00urn:sha1:affead9ad0a03ea9eecc80fe5e94e4e3b6090e74
Similar to the previous patch for VPCOM.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356344
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more2019-03-17T21:21:37+00:00Craig Toppercraig.topper@intel.com2019-03-17T21:21:37+00:00urn:sha1:12509d87f3a12dd7fb1fa34498b045439aa9fe0f
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
[X86] Strip the SAE bit from the rounding mode passed to the _RND opcodes. Use TargetConstant to save a conversion in the isel table.2019-03-15T19:59:35+00:00Craig Toppercraig.topper@intel.com2019-03-15T19:59:35+00:00urn:sha1:af856db9619339b267af82b381ef67b539ecaf50
The asm parser generates the immediate without the SAE bit. So for consistency we should generate the MCInst the same way from CodeGen.
Since they are now both the same, remove the masking from the printer and replace with an llvm_unreachable.
Use a target constant since we're rebuilding the node anyway. Then we don't have to have isel convert it. Saves about 500 bytes from the isel table.
llvm-svn: 356294