Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2018-05-22T13:24:38+00:00 2018-05-22T13:24:38+00:00 Aleksandar Beserminji Aleksandar.Beserminji@mips.com 2018-05-22T13:24:38+00:00 urn:sha1:a5f755186a7de274b35966c22dc57b4688ee2458 MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977 2018-05-21T11:38:52+00:00 Aleksandar Beserminji Aleksandar.Beserminji@mips.com 2018-05-21T11:38:52+00:00 urn:sha1:4977705727ed90cec32e72613b21a18509bc43ec Revert this patch due buildbot failure. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332837 2018-05-21T10:20:02+00:00 Aleksandar Beserminji Aleksandar.Beserminji@mips.com 2018-05-21T10:20:02+00:00 urn:sha1:de7be5e46f9eb3433fab194897859291e3dbc98f MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332834 2018-05-16T10:03:05+00:00 Simon Dardis simon.dardis@mips.com 2018-05-16T10:03:05+00:00 urn:sha1:5cf9de4b727b9311d5883fa682b1bd00b50647a8 Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446 2018-05-12T16:57:26+00:00 Simon Dardis simon.dardis@mips.com 2018-05-12T16:57:26+00:00 urn:sha1:65cc0cb31f32ae21f976a41fa0ae48b2028086ef llvm-svn: 332172 2018-05-09T02:42:00+00:00 Shiva Chen shiva0217@gmail.com 2018-05-09T02:42:00+00:00 urn:sha1:801bf7ebbed34577e730a53d6575035c26e39ac1 Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844 2018-05-01T13:06:49+00:00 Simon Dardis simon.dardis@mips.com 2018-05-01T13:06:49+00:00 urn:sha1:3d562fb9758599fe9ee5fee555a97e133a3c0613 The previous version of this patch restricted the 'jal' instruction to MIPS and microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal as an alias for balc. Original commit message: > Reviewers: smaksimovic, atanasyan, abeserminji > > Differential Revision: https://reviews.llvm.org/D46114 > llvm-svn: 331259 2018-04-30T14:03:35+00:00 Simon Dardis simon.dardis@mips.com 2018-04-30T14:03:35+00:00 urn:sha1:5a512d63c9b43bfaaf928789d423e25847fe4b4f That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178 2018-04-30T13:37:42+00:00 Simon Dardis simon.dardis@mips.com 2018-04-30T13:37:42+00:00 urn:sha1:cc95a9c5572cbae0788a2a4e94c29d61b504b1e7 Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175 2018-02-21T00:06:53+00:00 Simon Dardis simon.dardis@mips.com 2018-02-21T00:06:53+00:00 urn:sha1:7bc8ad5849f451589fe2d42a58155249df76879f This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653