Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-05-11T00:34:07+00:00 2019-05-11T00:34:07+00:00 Richard Trieu rtrieu@google.com 2019-05-11T00:34:07+00:00 urn:sha1:5e3ee4b84ef36fdf0b8f153de499cc024836a546 For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360490 2019-02-26T12:15:14+00:00 Igor Kudrin ikudrin@accesssoftek.com 2019-02-26T12:15:14+00:00 urn:sha1:2d3faad706c81814abc5e4080df38c4bccde1d48 The --disassembler-options, or -M, are used to customize the disassembler and affect its output. The two implemented options allow selecting register names on ARM: * With -Mreg-names-raw, the disassembler uses rNN for all registers. * With -Mreg-names-std it prints sp, lr and pc for r13, r14 and r15, which is the default behavior of llvm-objdump. Differential Revision: https://reviews.llvm.org/D57680 llvm-svn: 354870 2019-01-19T08:50:56+00:00 Chandler Carruth chandlerc@gmail.com 2019-01-19T08:50:56+00:00 urn:sha1:2946cd701067404b99c39fb29dc9c74bd7193eb3 to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636 2018-09-28T08:27:56+00:00 Oliver Stannard oliver.stannard@arm.com 2018-09-28T08:27:56+00:00 urn:sha1:5f34e9e265f87af4b5f1b64e885d5eaf58a904a2 This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300 2018-07-30T19:41:25+00:00 Fangrui Song maskray@google.com 2018-07-30T19:41:25+00:00 urn:sha1:f78650a8deca216b858827ff430972c114a60a7a sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338293 2018-07-06T08:03:12+00:00 Sjoerd Meijer sjoerd.meijer@arm.com 2018-07-06T08:03:12+00:00 urn:sha1:2a57b357a3a0de2202a3fb0272d2648a205bcdfa This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418 2018-03-29T22:31:36+00:00 David Blaikie dblaikie@gmail.com 2018-03-29T22:31:36+00:00 urn:sha1:bd0c88078a24e375fbd4611c1684cb811f7bd9ec llvm-svn: 328838 2018-03-06T15:21:19+00:00 Simi Pallipurath simi.pallipurath@arm.com 2018-03-06T15:21:19+00:00 urn:sha1:75c6bfeac9480c6f2877522f064e71dd4c43a6e9 This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 llvm-svn: 326803 2017-09-29T13:11:33+00:00 Sam Parker sam.parker@arm.com 2017-09-29T13:11:33+00:00 urn:sha1:963da5b1191f0ec084247252666d3f669fdaf71c New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511 2017-08-04T17:10:11+00:00 Javed Absar javed.absar@arm.com 2017-08-04T17:10:11+00:00 urn:sha1:9cda5991514db77774044816fd7fbf8897300231 This is a continuation of https://reviews.llvm.org/D36219 This patch uses reverse mapping (encoding->name) in ARMInstPrinter::printBankedRegOperand to get rid of hard-coded values (as pointed out by @olista01). Reviewed by: @fhahn, @rovka, @olista01 Differential Revision: https://reviews.llvm.org/D36260 llvm-svn: 310072