<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm5719-llvm/llvm/lib/Target/ARM/Disassembler, branch meklort-10.0.1</title>
<subtitle>Project Ortega BCM5719 LLVM</subtitle>
<id>https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1</id>
<link rel='self' href='https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/'/>
<updated>2020-01-15T03:46:52+00:00</updated>
<entry>
<title>CMake: Make most target symbols hidden by default</title>
<updated>2020-01-15T03:46:52+00:00</updated>
<author>
<name>Tom Stellard</name>
<email>tstellar@redhat.com</email>
</author>
<published>2020-01-15T03:15:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=0dbcb3639451a7c20e2d5133b459552281e64455'/>
<id>urn:sha1:0dbcb3639451a7c20e2d5133b459552281e64455</id>
<content type='text'>
Summary:
For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF
this change makes all symbols in the target specific libraries hidden
by default.

A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark symbols in these
libraries public, which is mainly needed for the definitions of the
LLVMInitialize* functions.

This patch reduces the number of public symbols in libLLVM.so by about
25%.  This should improve load times for the dynamic library and also
make abi checker tools, like abidiff require less memory when analyzing
libLLVM.so

One side-effect of this change is that for builds with
LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that
access symbols that are no longer public will need to be statically linked.

Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1):
nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l
36221
nm after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l
26278

Reviewers: chandlerc, beanz, mgorny, rnk, hans

Reviewed By: rnk, hans

Subscribers: merge_guards_bot, luismarques, smeenai, ldionne, lenary, s.egerton, pzheng, sameer.abuasal, MaskRay, wuzish, echristo, Jim, hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, kristina, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D54439
</content>
</entry>
<entry>
<title>[ARM][Thumb2] Fix ADD/SUB invalid writes to SP</title>
<updated>2020-01-14T11:47:19+00:00</updated>
<author>
<name>Diogo Sampaio</name>
<email>diogo.sampaio@arm.com</email>
</author>
<published>2020-01-13T11:36:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=d94d079a6a5b12156e4b818c8ba46eb143f335b9'/>
<id>urn:sha1:d94d079a6a5b12156e4b818c8ba46eb143f335b9</id>
<content type='text'>
Summary:
This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80".
The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable.
To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations.
When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant )
It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt).

Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb

Reviewed By: efriedma

Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70680
</content>
</entry>
<entry>
<title>[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()</title>
<updated>2020-01-11T21:34:52+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>maskray@google.com</email>
</author>
<published>2020-01-11T20:36:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=6fdd6a7b3f696972edc244488f59532d05136a27'/>
<id>urn:sha1:6fdd6a7b3f696972edc244488f59532d05136a27</id>
<content type='text'>
The argument is llvm::null() everywhere except llvm::errs() in
llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no
target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds.

If we ever have the needs to add verbose log to disassemblers, we can
record log with a member function, instead of passing it around as an
argument.
</content>
</entry>
<entry>
<title>Reverting, broke some bots. Need further investigation.</title>
<updated>2020-01-10T13:40:41+00:00</updated>
<author>
<name>Diogo Sampaio</name>
<email>diogo.sampaio@arm.com</email>
</author>
<published>2020-01-10T13:32:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=b1bb5ce96d349689085eab38121c85737de1fcaa'/>
<id>urn:sha1:b1bb5ce96d349689085eab38121c85737de1fcaa</id>
<content type='text'>
Summary: This reverts commit 8c12769f3046029e2a9b4e48e1645b1a77d28650.

Reviewers:

Subscribers:
</content>
</entry>
<entry>
<title>[ARM][Thumb2] Fix ADD/SUB invalid writes to SP</title>
<updated>2020-01-10T11:25:44+00:00</updated>
<author>
<name>Diogo Sampaio</name>
<email>diogo.sampaio@arm.com</email>
</author>
<published>2020-01-08T10:26:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=8c12769f3046029e2a9b4e48e1645b1a77d28650'/>
<id>urn:sha1:8c12769f3046029e2a9b4e48e1645b1a77d28650</id>
<content type='text'>
Summary:
This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80".
The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable.
To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations.
When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant )
It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt).

Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma

Reviewed By: efriedma

Subscribers: john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70680
</content>
</entry>
<entry>
<title>[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"</title>
<updated>2019-11-21T18:48:08+00:00</updated>
<author>
<name>Tom Stellard</name>
<email>tstellar@redhat.com</email>
</author>
<published>2019-11-14T05:39:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=ab411801b82783eb7f652701ccfce81b16cf1811'/>
<id>urn:sha1:ab411801b82783eb7f652701ccfce81b16cf1811</id>
<content type='text'>
Summary:
Most libraries are defined in the lib/ directory but there are also a
few libraries defined in tools/ e.g. libLLVM, libLTO.  I'm defining
"Component Libraries" as libraries defined in lib/ that may be included in
libLLVM.so.  Explicitly marking the libraries in lib/ as component
libraries allows us to remove some fragile checks that attempt to
differentiate between lib/ libraries and tools/ libraires:

1. In tools/llvm-shlib, because
llvm_map_components_to_libnames(LIB_NAMES "all") returned a list of
all libraries defined in the whole project, there was custom code
needed to filter out libraries defined in tools/, none of which should
be included in libLLVM.so.  This code assumed that any library
defined as static was from lib/ and everything else should be
excluded.

With this change, llvm_map_components_to_libnames(LIB_NAMES, "all")
only returns libraries that have been added to the LLVM_COMPONENT_LIBS
global cmake property, so this custom filtering logic can be removed.
Doing this also fixes the build with BUILD_SHARED_LIBS=ON
and LLVM_BUILD_LLVM_DYLIB=ON.

2. There was some code in llvm_add_library that assumed that
libraries defined in lib/ would not have LLVM_LINK_COMPONENTS or
ARG_LINK_COMPONENTS set.  This is only true because libraries
defined lib lib/ use LLVMBuild.txt and don't set these values.
This code has been fixed now to check if the library has been
explicitly marked as a component library, which should now make it
easier to remove LLVMBuild at some point in the future.

I have tested this patch on Windows, MacOS and Linux with release builds
and the following combinations of CMake options:

- "" (No options)
- -DLLVM_BUILD_LLVM_DYLIB=ON
- -DLLVM_LINK_LLVM_DYLIB=ON
- -DBUILD_SHARED_LIBS=ON
- -DBUILD_SHARED_LIBS=ON -DLLVM_BUILD_LLVM_DYLIB=ON
- -DBUILD_SHARED_LIBS=ON -DLLVM_LINK_LLVM_DYLIB=ON

Reviewers: beanz, smeenai, compnerd, phosek

Reviewed By: beanz

Subscribers: wuzish, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, mgorny, mehdi_amini, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, steven_wu, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, dang, Jim, lenary, s.egerton, pzheng, sameer.abuasal, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70179
</content>
</entry>
<entry>
<title>[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings</title>
<updated>2019-09-09T08:50:28+00:00</updated>
<author>
<name>Oliver Stannard</name>
<email>oliver.stannard@linaro.org</email>
</author>
<published>2019-09-09T08:50:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=6b9aedaec6815b819c626c5ba8d6fbbff9c6028c'/>
<id>urn:sha1:6b9aedaec6815b819c626c5ba8d6fbbff9c6028c</id>
<content type='text'>
Specify the Unpredictable bits, and return softfails when appropriate.

Patch by Mark Murray!

Differential revision: https://reviews.llvm.org/D66939

llvm-svn: 371374
</content>
</entry>
<entry>
<title>[ARM] MVE VPNOT</title>
<updated>2019-07-28T14:07:48+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2019-07-28T14:07:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=b8b8b46a5176d66981cf8a1898220a427d21535c'/>
<id>urn:sha1:b8b8b46a5176d66981cf8a1898220a427d21535c</id>
<content type='text'>
This adds the patterns required to transform xor P0, -1 to a VPNOT. The
instruction operands have to change a little for this, adding an in and an out
VCCR reg and using a custom DecodeMVEVPNOT for the decode.

Differential Revision: https://reviews.llvm.org/D65133

llvm-svn: 367192
</content>
</entry>
<entry>
<title>[ARM] Rename NEONModImm to VMOVModImm. NFC</title>
<updated>2019-07-23T09:19:24+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2019-07-23T09:19:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=fdedf240f8c9a64552329fb3d200165924013e90'/>
<id>urn:sha1:fdedf240f8c9a64552329fb3d200165924013e90</id>
<content type='text'>
Rename NEONModImm to VMOVModImm as it is used in both NEON and MVE.

llvm-svn: 366790
</content>
</entry>
<entry>
<title>[ARM] Add &lt;saturate&gt; operand to SQRSHRL and UQRSHLL</title>
<updated>2019-07-19T09:46:28+00:00</updated>
<author>
<name>Mikhail Maltsev</name>
<email>mikhail.maltsev@arm.com</email>
</author>
<published>2019-07-19T09:46:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/bcm5719-llvm/commit/?id=0b001f94a54a93e3e7ff080c829de8684f92630a'/>
<id>urn:sha1:0b001f94a54a93e3e7ff080c829de8684f92630a</id>
<content type='text'>
Summary:
According to the new Armv8-M specification
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf the
instructions SQRSHRL and UQRSHLL now have an additional immediate
operand &lt;saturate&gt;. The new assembly syntax is:

SQRSHRL&lt;c&gt; RdaLo, RdaHi, #&lt;saturate&gt;, Rm
UQRSHLL&lt;c&gt; RdaLo, RdaHi, #&lt;saturate&gt;, Rm

where &lt;saturate&gt; can be either 64 (the existing behavior) or 48, in
that case the result is saturated to 48 bits.

The new operand is encoded as follows:
  #64 Encoded as sat = 0
  #48 Encoded as sat = 1
sat is bit 7 of the instruction bit pattern.

This patch adds a new assembler operand class MveSaturateOperand which
implements parsing and encoding. Decoding is implemented in
DecodeMVEOverlappingLongShift.

Reviewers: ostannard, simon_tatham, t.p.northover, samparker, dmgreen, SjoerdMeijer

Reviewed By: simon_tatham

Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64810

llvm-svn: 366555
</content>
</entry>
</feed>
