bcm5719-llvm/llvm/lib/Target/ARM/ARMRegisterInfo.cpp, branch meklort-10.0.1 Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-01-19T08:50:56+00:00 Update the file headers across all of the LLVM projects in the monorepo 2019-01-19T08:50:56+00:00 Chandler Carruth chandlerc@gmail.com 2019-01-19T08:50:56+00:00 urn:sha1:2946cd701067404b99c39fb29dc9c74bd7193eb3 to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636 Remove the need to cache the subtarget in the ARM TargetRegisterInfo 2015-03-12T05:12:31+00:00 Eric Christopher echristo@gmail.com 2015-03-12T05:12:31+00:00 urn:sha1:34085832f8e7e86e328a1ae16fc41d7716a0c04d classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010 Prune includes in ARM target. 2014-03-22T23:51:00+00:00 Craig Topper craig.topper@gmail.com 2014-03-22T23:51:00+00:00 urn:sha1:a9253267a936a6b62b31567eb578e90f4669a4c3 llvm-svn: 204548 Don't cache the instruction and register info from the TargetMachine, because 2013-06-07T05:54:19+00:00 Bill Wendling isanbard@gmail.com 2013-06-07T05:54:19+00:00 urn:sha1:f95178e67956c1d71f71b7893fb01c9aac3fd691 the internals of TargetMachine could change. llvm-svn: 183488 Reorder includes to match coding standards. Fix an issue or two exposed by that. 2012-03-17T07:33:42+00:00 Craig Topper craig.topper@gmail.com 2012-03-17T07:33:42+00:00 urn:sha1:188ed9d56ecda032cbfd051d51cf2ec07c9e4f9d llvm-svn: 152978 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18T12:03:15+00:00 Jia Liu proljc@gmail.com 2012-02-18T12:03:15+00:00 urn:sha1:b22310fda63e03a80c808de5e0510339668820ea llvm-svn: 150878 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20T02:50:00+00:00 David Blaikie dblaikie@gmail.com 2011-12-20T02:50:00+00:00 urn:sha1:a379b181733b7ce77c9f336fd99e208d7c2a6f21 llvm-svn: 146960 Trim a few unneeded includes. 2011-04-18T21:35:54+00:00 Jim Grosbach grosbach@apple.com 2011-04-18T21:35:54+00:00 urn:sha1:ddac5dd269f7223857941afe9d29a3cccab9f083 llvm-svn: 129723 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10T12:39:04+00:00 Anton Korobeynikov asl@math.spbu.ru 2011-01-10T12:39:04+00:00 urn:sha1:2f9312810919ea7937327237aec6589fe0204ac0 llvm-svn: 123170 Generalize opcode selection in ARMBaseRegisterInfo. 2009-07-08T20:28:28+00:00 David Goodwin david_goodwin@apple.com 2009-07-08T20:28:28+00:00 urn:sha1:03ab0bbb2411e7e87e078e35842e553f706e66dc llvm-svn: 75036