Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2020-06-25T23:19:14+00:00 2020-06-25T23:19:14+00:00 Daniel Frampton Daniel.Frampton@microsoft.com 2020-03-31T20:12:54+00:00 urn:sha1:a110c3fc8cd9368627ce0386d7d16756be3d62ac The UnwindHelp object is used during exception handling by runtime code. It must be findable from a fixed offset from FP. This change allocates the UnwindHelp object as a fixed object (as is done for x86_64) to ensure that both the generated code and runtime agree on the location of the object. Fixes https://bugs.llvm.org/show_bug.cgi?id=45346 Differential Revision: https://reviews.llvm.org/D77016 (cherry picked from commit 494abe139a9aab991582f1b3f3370b99b252944c) 2020-06-25T23:19:14+00:00 Daniel Frampton Daniel.Frampton@microsoft.com 2020-03-31T20:11:16+00:00 urn:sha1:69fb858731e857abcabe74dcf6db344030ca650b The generated code for a funclet can have an add to sp in the epilogue for which there is no corresponding sub in the prologue. This patch removes the early return from emitPrologue that was preventing the sub to sp, and instead conditionalizes the appropriate parts of the rest of the function. Fixes https://bugs.llvm.org/show_bug.cgi?id=45345 Differential Revision: https://reviews.llvm.org/D77015 (cherry picked from commit 522b4c4b88a5606b0074926e8658e7fede97c230) 2020-06-17T22:37:19+00:00 Wei Zhao wxz@marvell.com 2020-05-13T23:38:42+00:00 urn:sha1:f5a9c661a35621640370837bae67cfb28f2f279b This is the first checkin to support Marvell ThunderX3T110. Initial definition of the micro-ops of the instructions in ThunderX3T110 is included. Differential Revision: https://reviews.llvm.org/D78129 (cherry picked from commit 382d3a85e2a9269569e7fb8caa487d7ef57900c6) 2020-06-17T03:05:15+00:00 Daniel Kiss daniel.kiss@arm.com 2020-06-15T13:02:38+00:00 urn:sha1:bf89c5aeb8915d488fa1c790e1b237b62a49c01f Summary: SCTLR_EL1.BT[01] controls the PACI[AB]SP compatibility with PBYTE 11 (see [1]) This bit will be set to zero so PACI[AB]SP are equal to BTI C instruction only. [1] https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/sctlr_el1 Reviewers: chill, tamas.petz, pbarrio, ostannard Reviewed By: tamas.petz, ostannard Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81746 (cherry picked from commit b8ae3fdfa579dbf366b1bb1cbfdbf8c51db7fa55) 2020-06-17T03:05:14+00:00 Daniel Kiss daniel.kiss@arm.com 2020-02-13T10:42:39+00:00 urn:sha1:aab50695971617d37ad420b476671995f7078e79 In some cases BTI landing pad is inserted even compatible instruction was there already. Meta instruction does not count in this case therefore skip them in the check for first instructions in the function. Differential revision: https://reviews.llvm.org/D74492 (cherry picked from commit d5a186a60014dc1a8c979c978cb32aba7ecb9102) 2020-02-18T15:46:42+00:00 John Brawn john.brawn@arm.com 2020-01-28T14:04:09+00:00 urn:sha1:cff417cffd61d2c4607eb142e272ec10ebec2c21 These get lowered to function calls, like the non-strict versions. Differential Revision: https://reviews.llvm.org/D73784 (cherry picked from commit 68cf574857c81f711f498a479855a17e7bea40f7) 2020-02-18T15:46:40+00:00 John Brawn john.brawn@arm.com 2020-01-27T15:51:06+00:00 urn:sha1:fca6c5e5dbf283b9e96b4a6ba8d343ff5dd91328 Strict fp-to-int and int-to-fp conversions can be handled in the same way that the non-strict versions are (by using the appropriate instruction or converting to a function call when we have no instruction). Differential Revision: https://reviews.llvm.org/D73625 (cherry picked from commit 0bb9a27c9895c0fbc3f55f56ad7f1e1927398fce) 2020-02-18T15:46:40+00:00 John Brawn john.brawn@arm.com 2020-01-21T17:18:18+00:00 urn:sha1:a97c77ad17502cc634473dc5ad433905f5d80b2f This gets selected to the appropriate fcvt instruction. Handling from there on isn't fully correct yet, as we need to model fcvt reading and writing to fpsr and fpcr. Differential Revision: https://reviews.llvm.org/D73201 (cherry picked from commit 258d8dd76afd88a12539b182a53ff21dcba16a2d) 2020-02-18T15:46:39+00:00 John Brawn john.brawn@arm.com 2020-01-24T15:47:51+00:00 urn:sha1:f87a0929c6bd59750e424d06581507cdfd439a56 These become STRICT_FCMP and STRICT_FCMPE, which then get selected to the corresponding FCMP and FCMPE instructions, though the handling from there on isn't fully correct as we don't model reads and writes to FPCR and FPSR. Differential Revision: https://reviews.llvm.org/D73368 (cherry picked from commit 2224407ef5baf6100fa22420feb4d25af1a9493f) 2020-02-10T13:28:36+00:00 Florian Hahn florian_hahn@apple.com 2020-01-27T23:11:45+00:00 urn:sha1:b8fead783fa19d48a2e2c3162fba5271360f57b5 This patch adds a new option to enable/disable register renaming in the load-store optimizer. Defaults to disabled, as there is a potential mis-compile caused by this. (cherry picked from commit 8e3f59b45ae185cc9b4e3a817d7ac958f1d55976)