bcm5719-llvm/llvm/lib/MCA/HardwareUnits, branch meklort-10.0.1Project Ortega BCM5719 LLVMhttps://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.12020-01-01T19:01:37+00:00[NFC] Fixes -Wrange-loop-analysis warnings2020-01-01T19:01:37+00:00Mark de Weverkoraq@xs4all.nl2020-01-01T16:23:21+00:00urn:sha1:8dc7b982b4556c243e0502e6e230bdd53ddd65ff
This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall.
Differential Revision: https://reviews.llvm.org/D71857
[MCA][LSUnit] Track loads and stores until retirement.2019-10-08T10:46:01+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-10-08T10:46:01+00:00urn:sha1:8d6651f7b11ee3bc68d4e5523e44e987b53760bf
Before this patch, loads and stores were only tracked by their corresponding
queues in the LSUnit from dispatch until execute stage. In practice we should be
more conservative and assume that memory opcodes leave their queues at
retirement stage.
Basically, loads should leave the load queue only when they have completed and
delivered their data. We conservatively assume that a load is completed when it
is retired. Stores should be tracked by the store queue from dispatch until
retirement. In practice, stores can only leave the store queue if their data can
be written to the data cache.
This is mostly a mechanical change. With this patch, the retire stage notifies
the LSUnit when a memory instruction is retired. That would triggers the release
of LDQ/STQ entries. The only visible change is in memory tests for the bdver2
model. That is because bdver2 is the only model that defines the load/store
queue size.
This patch partially addresses PR39830.
Differential Revision: https://reviews.llvm.org/D68266
llvm-svn: 374034
[MCA] Use references to LSUnitBase in class Scheduler and add helper methods to acquire/release LS queue entries. NFCI2019-09-30T17:24:25+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-09-30T17:24:25+00:00urn:sha1:2730df2e164b9a1f98cebd2dd51f059650fcec27
llvm-svn: 373236
[Tblgen][MCA] Add the ability to mark groups as LoadQueue and StoreQueue. NFCI2019-08-27T18:20:34+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-08-27T18:20:34+00:00urn:sha1:2f51a43f8c2b117e69a45eae6a7c849e035a793b
Before this patch, users were not allowed to optionally mark processor resource
groups as load/store queues. That is because tablegen class MemoryQueue was
originally declared as expecting a ProcResource template argument (instead of a
more generic ProcResourceKind).
That was an oversight, since the original intention from D54957 was to let user
mark any processor resource as either load/store queue. This patch adds the
ability to use processor resource groups in MemoryQueue definitions. This is not
a user visible change.
Differential Revision: https://reviews.llvm.org/D66810
llvm-svn: 370091
[MCA] consistently use MCPhysReg instead of unsigned as register type. NFCI2019-08-22T13:32:17+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-08-22T13:32:17+00:00urn:sha1:589cb004dee799a097b878a8a13e4ba43114d5bd
llvm-svn: 369648
[llvm] Migrate llvm::make_unique to std::make_unique2019-08-15T15:54:37+00:00Jonas Devliegherejonas@devlieghere.com2019-08-15T15:54:37+00:00urn:sha1:0eaee545eef49ff9498234d3a51a5cbde59bf976
Now that we've moved to C++14, we no longer need the llvm::make_unique
implementation from STLExtras.h. This patch is a mechanical replacement
of (hopefully) all the llvm::make_unique instances across the monorepo.
llvm-svn: 369013
[MCA] Slightly refactor class RetireControlUnit, and add the ability to override the mask of used buffered resources in class mca::Instruction. NFCI2019-08-15T15:27:40+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-08-15T15:27:40+00:00urn:sha1:3de2f0330f4b7b4b099b21a030e19c442f536a83
This patch teaches the RCU how to peek 'next' RCUTokens. A new method has been
added to the RetireControlUnit class with the goal of minimizing the complexity
of follow-up patches that will enable macro-fusion support in mca.
This patch also adds method Instruction::getNumMicroOpcodes() to simplify common
interactions with the instruction descriptor (a pattern quite common in some
pipeline stages).
Added the ability to override the default set of consumed scheduler resources
(this -again- is to simplify future patches that add support for macro-op fusion).
No functional change intended.
llvm-svn: 369010
[MCA] Slightly refactor the logic in ResourceManager. NFCI2019-08-15T12:39:55+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-08-15T12:39:55+00:00urn:sha1:7aa0dbb664ea05e233c503c009052f8682fc0f62
This patch slightly changes the API in the attempt to simplify resource buffer
queries. It is done in preparation for a patch that will enable support for
macro fusion.
llvm-svn: 368994
[MCA] Further refactor the bottleneck analysis view. NFCI.2019-06-10T12:50:08+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-06-10T12:50:08+00:00urn:sha1:47db08dbb19cc326e7002b0068237e1b92bd529e
llvm-svn: 362933
[MCA][Scheduler] Change how memory instructions are dispatched to the pending set. NFCI2019-06-01T15:22:37+00:00Andrea Di BiagioAndrea_DiBiagio@sn.scee.net2019-06-01T15:22:37+00:00urn:sha1:6a989c358cc79928a8cff0b51913d11417866dc4
llvm-svn: 362302