Project Ortega BCM5719 LLVM https://git.raptorcs.com/git/bcm5719-llvm/atom?h=meklort-10.0.1 2019-12-16T16:36:56+00:00 2019-12-16T16:36:56+00:00 Sam Elliott selliott@lowrisc.org 2019-12-16T16:35:17+00:00 urn:sha1:ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e Summary: Add unwinding support for 64-bit RISC-V. This is from the FreeBSD implementation with the following minor changes: - Renamed and renumbered DWARF registers to match the RISC-V ABI [1] - Use the ABI mneumonics in getRegisterName() instead of the exact register names - Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit ABI in the future. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md Patch by Mitchell Horne (mhorne) Reviewers: lenary, luismarques, compnerd, phosek Reviewed By: lenary, luismarques Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D68362 2019-04-11T16:37:07+00:00 Louis Dionne ldionne@apple.com 2019-04-11T16:37:07+00:00 urn:sha1:2b0da3d63ea6281d7ae8f858bbf86270a5405fb1 Those are now hosted on GitHub. rdar://problem/36557462 llvm-svn: 358191 2019-02-02T20:54:03+00:00 Petr Hosek phosek@chromium.org 2019-02-02T20:54:03+00:00 urn:sha1:368c02e3ec44e5418626f46abebcc22a69c7f66d This is unfinished, unused and incomplete. This could be brought back in the future if there's a desire to build a more complete implementation, but at the moment it's just bitrotting. Differential Revision: https://reviews.llvm.org/D57252 llvm-svn: 352965 2019-01-29T09:00:32+00:00 Martin Storsjo martin@martin.st 2019-01-29T09:00:32+00:00 urn:sha1:d27bec48542e9638ff41033ad714e90207b53c68 The existing typedef of unw_fpreg_t to uint64_t might work and be correct for the ARM_EHABI case, but for dwarf, some cases in e.g. DwarfInstructions.hpp convert between double and unw_fpreg_t. When converting implicitly between double and unw_fpreg_t (uint64_t), the values get interpreted as integers and converted to float and vice versa, while the correct thing would be to keep the same bit pattern. Avoid the whole issue by using the same definition of unw_fpreg_t as all other architectures, when using dwarf unwinding on ARM. Change assembler functions to take a void pointer instead of unw_fpreg_t pointer, to avoid having a different mangled symbol name depending on the actual value of this typedef. Differential Revision: https://reviews.llvm.org/D57001 llvm-svn: 352461 2019-01-19T10:56:40+00:00 Chandler Carruth chandlerc@gmail.com 2019-01-19T10:56:40+00:00 urn:sha1:57b08b0944046a6a57ee9b7b479181f548a5b9b4 to reflect the new license. These used slightly different spellings that defeated my regular expressions. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351648 2019-01-14T10:15:20+00:00 Daniel Cederman cederman@gaisler.com 2019-01-14T10:15:20+00:00 urn:sha1:17121adfa607b1d70300e88925767626333cf730 Summary: Adds the register class implementation for Sparc. Adds support for DW_CFA_GNU_window_save. Adds save and restore context functionality. Adds getArch() function to each Registers_ class to be able to separate between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which are both represented by the same constant. On Sparc the return address is the address of the call instruction, so an offset needs to be added when returning to skip the call instruction and its delay slot. If the function returns a struct it is also necessary to skip one extra instruction on Sparc V8. Reviewers: jyknight, mclow.lists, mstorsjo, compnerd Reviewed By: jyknight, compnerd Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits Differential Revision: https://reviews.llvm.org/D55763 llvm-svn: 351044 2019-01-10T01:08:31+00:00 Jorge Gorbe Moya jgorbe@google.com 2019-01-10T01:08:31+00:00 urn:sha1:8d530b777d5332ebc1fbf8239865dc1f507e740c This reverts commit r350705. llvm-svn: 350787 2019-01-09T12:06:05+00:00 Daniel Cederman cederman@gaisler.com 2019-01-09T12:06:05+00:00 urn:sha1:b2be18f42dd8f5b0e20c6c3c3a186716ec70191f Summary: Adds the register class implementation for Sparc. Adds support for DW_CFA_GNU_window_save. Adds save and restore context functionality. On Sparc the return address is the address of the call instruction, so an offset needs to be added when returning to skip the call instruction and its delay slot. If the function returns a struct it is also necessary to skip one extra instruction. Reviewers: jyknight, mclow.lists, mstorsjo, compnerd Reviewed By: compnerd Subscribers: fedor.sergeev, JDevlieghere, ldionne, libcxx-commits Differential Revision: https://reviews.llvm.org/D55763 llvm-svn: 350705 2018-12-18T20:05:59+00:00 Martin Storsjo martin@martin.st 2018-12-18T20:05:59+00:00 urn:sha1:09cf6374c162b13e00bb86c10e6e481abf437a07 This doesn't yet implement inspecting the .pdata/.xdata to find the LSDA pointer (in UnwindCursor::getInfoFromSEH), but normal C++ exception handling seems to run just fine without it. (The only place I can see where it's even referenced is in unwind_phase2_forced, and I can't find a codepath where libcxxabi would end up calling that.) Differential Revision: https://reviews.llvm.org/D55674 llvm-svn: 349532 2018-12-14T11:30:12+00:00 Luke Cheeseman luke.cheeseman@arm.com 2018-12-14T11:30:12+00:00 urn:sha1:e1a819e82de87bfd217d73ca74a39d10b46d0a71 - Follow up to revision r342895 - gcc would not build libunwind with the earlier patch as the autia1716 instruction wasn't allowed to be assembled for pre armv8.3a targets - The autia1716 instruction lives in the hint space encodings so is a valid instruction for all armv8a targets - To work around this I have swapped out the autia1716 instruction for the hint instruction Differential Revision: https://reviews.llvm.org/D55700 llvm-svn: 349140