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-rw-r--r--arch/Config.in.mips31
1 files changed, 20 insertions, 11 deletions
diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 3662fedca8..ce41e9e725 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -47,22 +47,31 @@ config BR2_mips_interaptiv
bool "interAptiv"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
-config BR2_mips_m5100
- bool "M5100"
+config BR2_mips_m5150
+ bool "M5150"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
-config BR2_mips_m5101
- bool "M5101"
- depends on !BR2_ARCH_IS_64
- select BR2_MIPS_CPU_MIPS32R5
-config BR2_mips_m6201
- bool "M6201"
+config BR2_mips_m6250
+ bool "M6250"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R6
config BR2_mips_p5600
bool "P5600"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
+config BR2_mips_xburst
+ bool "XBurst"
+ depends on !BR2_ARCH_IS_64
+ select BR2_MIPS_CPU_MIPS32R2
+ help
+ The Ingenic XBurst is a MIPS32R2 microprocessor. It has a
+ bug in the FPU that can generate incorrect results in
+ certain cases. The problem shows up when you have several
+ fused madd instructions in sequence with dependant
+ operands. This requires the -mno-fused-madd compiler option
+ to be used in order to prevent emitting these instructions.
+
+ See http://www.ingenic.com/en/?xburst.html
config BR2_mips_64
bool "Generic MIPS64"
depends on BR2_ARCH_IS_64
@@ -133,10 +142,10 @@ config BR2_GCC_TARGET_ARCH
default "mips32r5" if BR2_mips_32r5
default "mips32r6" if BR2_mips_32r6
default "interaptiv" if BR2_mips_interaptiv
- default "m5100" if BR2_mips_m5100
- default "m5101" if BR2_mips_m5101
- default "m6201" if BR2_mips_m6201
+ default "m5101" if BR2_mips_m5150
+ default "m6201" if BR2_mips_m6250
default "p5600" if BR2_mips_p5600
+ default "mips32r2" if BR2_mips_xburst
default "mips64" if BR2_mips_64
default "mips64r2" if BR2_mips_64r2
default "mips64r5" if BR2_mips_64r5
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